*******************************************************
i++ debug log file
This file contains diagnostic information. Any errors
or unexpected behavior encountered when running i++
should be reported as bugs. Thank you.
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Compiler Command: i++ -march=Arria10 counter.cpp -o test-fpga.exe
2019.01.14.16:23:17 Info: Doing: qsys-script --script=count.tcl --quartus-project=none
2019.01.14.16:23:21 Info: create_system count
2019.01.14.16:23:21 Info: set_project_property HIDE_FROM_IP_CATALOG false
2019.01.14.16:23:21 Info: set_project_property DEVICE_FAMILY Arria10
2019.01.14.16:23:21 Info: Info: The device and speed grade is changed to the defaults of the device family, Arria10.
2019.01.14.16:23:21 Info: set_project_property DEVICE 10AX115U1F45I1SG
2019.01.14.16:23:21 Info: add_instance count_internal_inst count_internal
2019.01.14.16:23:22 Info: set_instance_property count_internal_inst AUTO_EXPORT true
2019.01.14.16:23:22 Info: save_system count.ip
2019.01.14.16:23:29 Info: Saving generation log to C:/intelFPGA_pro/18.1/hls/examples/counter/test-fpga.prj/components/count/count/count_generation.rpt
2019.01.14.16:23:29 Info: Generated by version: 18.1 build 222
2019.01.14.16:23:29 Info: Starting: Create HDL design files for synthesis
2019.01.14.16:23:29 Info: qsys-generate C:\intelFPGA_pro\18.1\hls\examples\counter\test-fpga.prj\components\count\count.ip --synthesis=VERILOG --output-directory=C:\intelFPGA_pro\18.1\hls\examples\counter\test-fpga.prj\components\count\count --family="Cyclone 10 GX" --part=Unknown
2019.01.14.16:23:29 Warning: count_internal_inst: Invalid device family name in input file: Arria 10
2019.01.14.16:23:29 Warning: count_internal_inst: Invalid device name in input file: 10AX115U1F45I1SG
2019.01.14.16:23:29 Error: count: Component count_internal_inst does not support selected device family Cyclone 10 GX
2019.01.14.16:23:29 Error: qsys-generate failed with exit code 3: 1 Error, 2 Warnings
2019.01.14.16:23:29 Info: Finished: Create HDL design files for synthesis
2019.01.14.16:23:29 Info: Starting: IP-XACT
2019.01.14.16:23:29 Info: qsys-generate C:\intelFPGA_pro\18.1\hls\examples\counter\test-fpga.prj\components\count\count.ip --synthesis=VERILOG --ipxact --output-directory=C:\intelFPGA_pro\18.1\hls\examples\counter\test-fpga.prj\components\count\count --family="Cyclone 10 GX" --part=Unknown
2019.01.14.16:23:29 Info: Finished: IP-XACT
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