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Mads_From_Denmark
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5 days ago
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AI Suite - Various Questions

Hello Altera Community
I have a few questions about the AI Suite

1. Estimating whether a model will fit on an FPGA using a formula

Suppose I have a neural network with x amount of layers and y amount of neurons in each layer.
Then say I have a baord with an amount of DSP/ALMs/LUTs

What could be an approximating formula (It does not need to be accurate). And what are the typical limiting factors?

2. Impact of the enable_parameter_rom parameter

Is it correctly understood that this parameter determines whatever the mif (Memory initialization files) containing the weights are put inside a rom or external memory?

Does this actually impact the speed? I would assume that the external memory might be faster than some of the bottleneck components in the AI IP block.

3. Any architecture options for the Spatial IP?

My model uses a 16bf * 6 input, so I think it would make sense to increase the input stream size so it matches. But I don't know if the same options from the sequential IP also applies to the spatial IP, since the example is just two lines.

  • 1. Estimating whether a model will fit on an FPGA using a formula

    What could be an approximating formula (It does not need to be accurate). And what are the typical limiting factors?

    You can run the dla_compiler to get the resources utilization  base on https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/estimating-the-area-and-power-of-an-architecture

    2. Impact of the enable_parameter_rom parameter

    Is it correctly understood that this parameter determines whatever the mif (Memory initialization files) containing the weights are put inside a rom or external memory?
    This function is depreciated. Use enable_on_chip_parameters and disable_external_memory instead. This will disable the use of external memory

    Does this actually impact the speed? I would assume that the external memory might be faster than some of the bottleneck components in the AI IP block.

    Yes, but will increase the M20K utilziation

    3. Any architecture options for the Spatial IP?

    My model uses a 16bf * 6 input, so I think it would make sense to increase the input stream size so it matches. But I don't know if the same options from the sequential IP also applies to the spatial IP, since the example is just two lines.
    Please refer to 
    $COREDLA_ROOT/example_architectures/AGX5_Simple_Spatial.arch

    • $COREDLA_ROOT/example_architectures/AGX7_Robust_Spatial_Compilation.arch
    • $COREDLA_ROOT/example_architectures/AGX7_Simple_Spatial.arch

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  • JohnT_Altera's avatar
    JohnT_Altera
    Icon for Regular Contributor rankRegular Contributor

    1. Estimating whether a model will fit on an FPGA using a formula

    What could be an approximating formula (It does not need to be accurate). And what are the typical limiting factors?

    You can run the dla_compiler to get the resources utilization  base on https://docs.altera.com/r/docs/863373/2026.1.1/fpga-ai-suite-handbook/estimating-the-area-and-power-of-an-architecture

    2. Impact of the enable_parameter_rom parameter

    Is it correctly understood that this parameter determines whatever the mif (Memory initialization files) containing the weights are put inside a rom or external memory?
    This function is depreciated. Use enable_on_chip_parameters and disable_external_memory instead. This will disable the use of external memory

    Does this actually impact the speed? I would assume that the external memory might be faster than some of the bottleneck components in the AI IP block.

    Yes, but will increase the M20K utilziation

    3. Any architecture options for the Spatial IP?

    My model uses a 16bf * 6 input, so I think it would make sense to increase the input stream size so it matches. But I don't know if the same options from the sequential IP also applies to the spatial IP, since the example is just two lines.
    Please refer to 
    $COREDLA_ROOT/example_architectures/AGX5_Simple_Spatial.arch

    • $COREDLA_ROOT/example_architectures/AGX7_Robust_Spatial_Compilation.arch
    • $COREDLA_ROOT/example_architectures/AGX7_Simple_Spatial.arch