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jjb169's avatar
jjb169
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4 months ago

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

Hello, I've been working through the Open FPGA Stack (OFS) guides to set up my Agilex 7 I-Series development kit for use with oneAPI. I've worked through prior SystemVerilog issues encountered by sw...
JohnT_Altera's avatar
JohnT_Altera
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1 month ago

Hi,

 

Can you try the PCIe 1x16 design rather than 2x8?

jjb169's avatar
jjb169
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1 month ago

Hello,

I initially tried to build a 1x16 design, but ran into the SystemVerilog errors which are shown in the text file attached to this response. This issue was also discussed in a similar forum post (link). Building a 2x8 configuration design avoided these errors, which is why I've been using that style so far.

Let me know what you think, or if there is a specific compilation script you would like me to run that may help solve these errors.

Thank you!

James