New Contributor
New Contributor> Do you have a board in mind? Keep in mind that if you wish to use
> oneAPI FPGA Acceleration, you should choose an acceleration card
> with a supported BSP. We have a list of vendor cards on our
> homepage:
Yeah, the board is a DE10 Agilex 7 from Terasic. The exact model is
AGF 7 014 B2E2_8GBx4.
> Instead of building a full oneAPI BSP, you can also use the oneAPI
> DPC++/C++ compiler to create IP that you can integrate using a
> platform designer system.
Well, I have a server license for Quartus Prime 21.2. Previously I
have used the aoc (Intel(R) FPGA SDK for OpenCL(TM) Kernel Compiler)
command to build FPGA bitstreams from OpenCL code so I think I already
have a suitable BSP installed. What I'm missing is how to "connect"
icpx (Intel(R) oneAPI DPC++/C++ Compiler) to the FPGA. It was easy
with OpenCL. I just compiled the kernel with aoc and then loaded it
onto the FPGA with OpenCL host code. It appears it is not that easy
with SYCL.
ContributorThere is an additional step; with OpenCL (and indeed, earlier versions of oneAPI) we shipped some popular BSPs along with the tools, but since 2022 we stopped that to limit the installation size. You should be able to get a BSP from Terasic (indeed it should have been provided when you purchased it). Once you install the BSP, you can point the compiler to it when you compile your code. We explain how to do this in the code samples.
FYI: that BSP depends on an older version of Quartus, and unless Terasic updates the BSP, it will fall out of the support window.
