Adding an Avalon FIFO IP with PCIeDMA Transfer Example design (Provided in CD) for Arria 10 GX FPGA

Hi travisa,

There is another thread that has been created with similar description on https://community.intel.com/t5/FPGA-Intellectual-Property/Integrating-a-Avalon-FIFO-IP-to-the-PCIe-DMA-transfer-example/m-p/1427485#M26591

Please post your related question in previous thread. This thread will be transitioned to community support.

Thank you.