Forum Discussion
travisa
New Contributor
New ContributorAdding an Avalon FIFO IP with PCIeDMA Transfer Example design (Provided in CD) for Arria 10 GX FPGA
Hi,
I am trying to stream in data from an external source (through QSFP+) to the DDR4 memory and then do a DMA transfer the data to a Computer through PCIe.
For that I would like to use a FIFO ...
AdzimZM_Altera
Regular Contributor
Regular ContributorHi travisa,
There is another thread that has been created with similar description on https://community.intel.com/t5/FPGA-Intellectual-Property/Integrating-a-Avalon-FIFO-IP-to-the-PCIe-DMA-transfer-example/m-p/1427485#M26591
Please post your related question in previous thread. This thread will be transitioned to community support.
Thank you.
