Forum Discussion

Occasional Contributor

5 years ago

Achieving parallel execution of loop on FPGA

I am having difficulty persuading the compiler to execute an outer loop in parallel in an FPGA kernel. I have constructed a simple example to illustrate the issue. Here is a simple array initialisa...

AnilErinch_A_Intel

Frequent Contributor

5 years ago

Hi ,

Can you try to unroll the internal loop and use IVDEP on the outer loop of the manually inverted code snippet and see the effect it has on the performance.

Please refer to the line number 55 of the ivdep example given below.

https://github.com/oneapi-src/oneAPIsamples/blob/master/DirectProgramming/DPC%2B%2BFPGA/Tutorials/Features/loop_ivdep/src/loop_ivdep.cpp

Thanks and Regards

Anil

Forum Discussion

Achieving parallel execution of loop on FPGA

Recent Discussions

This is a test post

Agilex 7 M series Open FPGA Stack support

Deprecation Notice for FPGA Support Package for oneAPI DPC++/C++. What is the alternative?

Agilex 7 I-Series "aocl diagnose acl0" error following OFS

OneAPI Support for Agilex 5 and 7 Development Kits