Forum Discussion
Mickleman
Occasional Contributor
Occasional ContributorAchieving parallel execution of loop on FPGA
I am having difficulty persuading the compiler to execute an outer loop in parallel in an FPGA kernel. I have constructed a simple example to illustrate the issue.
Here is a simple array initialisa...
AnilErinch_A_Intel
Frequent Contributor
Frequent ContributorHi ,
Can you try to unroll the internal loop and use IVDEP on the outer loop of the manually inverted code snippet and see the effect it has on the performance.
Please refer to the line number 55 of the ivdep example given below.
Thanks and Regards
Anil
