Forum Discussion

Mickleman's avatar
Mickleman
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Achieving parallel execution of loop on FPGA

I am having difficulty persuading the compiler to execute an outer loop in parallel in an FPGA kernel. I have constructed a simple example to illustrate the issue. Here is a simple array initialisa...
Mickleman's avatar
Mickleman
Icon for Occasional Contributor rankOccasional Contributor
5 years ago

Thanks @MGRAV

I'm not sure I quite understand what you are suggesting. If you could give me a version of the example changed as you propose I will try it out and feed back the results.

Regards

MGRAV's avatar
MGRAV
Icon for New Contributor rankNew Contributor
5 years ago

maybe something like this, and even I don't know if the compiler can figure out

const int ITEM_LENGTH = 10000;
const int GROUP_SIZE = 10;
uint16_t a[ITEM_LENGTH][GROUP_SIZE];
uint16_t b[ITEM_LENGTH][GROUP_SIZE];

[[intel::ivdep]]
for (int k = 0; k < GROUP_SIZE * ITEM_LENGTH; k++)
{
int i = k / GROUP_SIZE;
int j = k - i * GROUP_SIZE;

if ( i == 0 )
a[i][j] = j;
else
a[i][j] = a[i-1][j] + i;
}

[[intel::ivdep]]
for (int k = 0; k < GROUP_SIZE * ITEM_LENGTH; k++)
{
int i = k / GROUP_SIZE;
int j = k - i * GROUP_SIZE;

if ( i == 0 )
b[i][j] = j;
else
b[i][j] = b[i-1][j] + i;
}

But what the problem with the two loops if it work ?