Forum Discussion

Mickleman's avatar
Mickleman
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Achieving parallel execution of loop on FPGA

I am having difficulty persuading the compiler to execute an outer loop in parallel in an FPGA kernel. I have constructed a simple example to illustrate the issue. Here is a simple array initialisa...
MGRAV's avatar
MGRAV
Icon for New Contributor rankNew Contributor
4 years ago

Hi @Mickleman,

I am not sure but I assume that is the way you get you i and j out of the division and the modulo.

I imagine you rewrite as follow (that do basically the same, without branching)

uint16_t* c=(uint16_t*)a

bool test=(k<GROUP_SIZE) ;

int i=k / GROUP_SIZE;

c[k]= (c[k-1]+i)*(!test)+(test)* (k-i*GROUP_SIZE);

you can get that the compiler don't see the opportunity over the GROUP_SIZE parallelization.

I think to get it automatically you should permute you array, a[j][i] ==> a[i][j] so the dependency inside look like c[k-GROUP_SIZE].

I don't know if I am clear in what I mean

Mickleman's avatar
Mickleman
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Thanks @MGRAV

I'm not sure I quite understand what you are suggesting. If you could give me a version of the example changed as you propose I will try it out and feed back the results.

Regards