Most RecentWhy are the VOD, pre-emphasis, and slew rate parameters reported as -1 for Stratix® V, Arria® V, and Cyclone® V FPGA transceiver pins in the Resource Property Editor when using Quartus® II software version 13.0 and 13.0sp1?What is the number of non-transceiver PLLs for the Stratix® II GX 60C and EP2SGX60D devices?TCP DSTREAM Connection Fails with Trace EnabledWhy are my output pins not recognized in Quartus® Pin Planner after Analysis & Synthesis?Why does the reset_status signal not respond when the npor signal is deasserted in the Avalon®-ST Intel® Stratix® 10 Hard IP for PCI* Express?What I/O standard should I use when driving signals over long lengths of cable?Internal Error: Sub-system: LCHIP, File: /quartus/legality/lchip/lchip_rowclock_router.cpp, Line: 1011Why do the 25G Ethernet Intel® Arria® 10 FPGA IP core, Intel® 50 Gbps Ethernet (50GbE) IP core, and the 25G Ethernet Intel® Stratix® 10 FPGA IP core incorrectly report oversized frames for VLAN and Stacked VLAN Tagged frames?DDR2 Interfaces on Cyclone V SoC Devices May Fail Read Capture TimingError (13119): Channels xxx are driven by X1 clock network and need to be placed in the same six-pack due to user location constraints. However, only 2 of the six-pack channels are usable.
