Most RecentWhy do I see a "System.xcvr: "Number of lanes" (lanes) (1) out of range (1,0)" Qsys error when upgrading Stratix IV GX and Arria II GX transceiver toolkit designs between different versions of the Quartus II software?Stratix IV Pin Connection Guidelines: Known IssuesWhy is the ready allowance smaller than the read latency of RX and TX Avalon® Streaming interfaces in the Arria® 10 Hard IP for PCI Express?What is the last version of the Quartus II software to support SOPC Builder?Why is the reset controller not behaving correctly when performing a reset via the Avalon®-MM interface in the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP?How can I erase all non-volatile memories on the Intel® Stratix® 10 SX SoC Development Kit?Why isn't the F-Tile Transceiver Toolkit visible when using the F-Tile PMA/FEC Direct PHY Multirate IP?Why does the F-Tile JESD204C Agilex™ 7 FPGA IP Design Example Generation fail when the data rate is between 16.3 Gbps and 17.1 Gbps?Error importing a valid value. Field "Operation Mode" will be set to default value.Why is timing performance degraded for Qsys-generated logic in the Quartus II software version 13.0 compared with earlier versions?
