Why is the reset controller not behaving correctly when performing a reset via the Avalon®-MM interface in the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP?

Description

Due to a problem with the code generation for the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP version 18.0 an incorrect connection is made in the file alt_ehipc3_sl_soft.sv for the reset controller. 

Resolution

To work around this problem, perform the following changes in the file <IP Folder>/alt_ehipc3_180/synth/alt_ehipc3_sl_soft.sv:

From:

            .soft_tx_rst_in            (i_sl_soft_csr_rst),

            .soft_rx_rst_in            (i_sl_soft_tx_rst),

            .soft_csr_rst_in           (i_sl_soft_rx_rst),

To:

            .soft_tx_rst_in            (i_sl_soft_tx_rst),

            .soft_rx_rst_in            (i_sl_soft_rx_rst),

            .soft_csr_rst_in           (i_sl_soft_csr_rst),

This problem has been fixed starting in v18.0.1 of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP.