Most RecentWhy do I see the message Info: <system name>: There are recommended upgrades for: pcie_<device>_hip__0 Even though the Qsys system was upgraded?Internal Error: Sub-system: PTI, File: /quartus/tsm/pti/pti_tdb_builder.cpp, Line: 1315Can I use the Altera® vendor ID as the vendor ID for a PCI interface?What are the options to download and install the Altera Complete Design Suite (ACDS) version 10.0?Why do I see *rx_prbs_err_snapshot[*] snapshot register hold time violations in TimeQuest when compiling an Arria 10 device Native PHY IP in Quartus Prime software version 15.1.2 and earlier?Scaler: Number of Colour Planes IncorrectWhy does the RTL from my insert template not appear in the expected VHDL/Verilog HDL file?Why does IP Upgrade fail on a composed IP that includes the discontinued Nios® II processor IP in future Quartus® Prime Software?Why I can not generate PCI compiler with Stratix V device ?Error(11997): Design has 55 tx channels, 9 rx channels, exceeds the capacity of targeted device, 48 channels
