Most RecentError (10386): VHDL error : non-constant index is always outside the rangePlatform designer automatic interconnect bandwidth behaviorHi, this is on stratix board MX. I am unable to generate HDL for esram block from platform designer. error details are given below. Anybody knows whats the wrong with this IP ?What is the script equivalent of Quartus Prime GUI's "Export Report as HTML"?How to properly set up a stratix 10 transceiver in Quartus 17.1How to eliminate sporadic errors on Stratix-V designs?Driver and associated documentation to interface to PCIe Hard IP for Cyclone VHello, I am using a Altera Stratix® V GX FPGA (5SGXEA7N2F45C2). The default clock frequency is 50MHz. I am using the pin PIN_AW35. Can I change the clock frequency? What is the maximum limit? ThanksCan't route signal to atom for simple ADC PLLI have Quartus II 13.0.1 web edition? When I try to simulate using University Program WMF the end time is limited to 100us. How can extend it? I saw in tutorials that it is not limited.
