Most RecentDowngrade IPs -> possible?dummy content for moveHello, I have a DE10-Lite board that I am trying to convert BCD to Decimal. Hear is my code and I am having issues getting is to work, can you see where I'm going wrong?Hello, I am writing a verilog code from my DE10-Lite Board to scroll the a word or number but keep having errors. Would you be able to help?How can I solve this problem?VHDL pragma --synthesis library ... is unsupported in 20.1 ?Error: Third-party timing and resource estimation model project creation failed (Quartus 20.1)I am almost certain that my Quartus II web 13.1 program creates RTL schematics with errors in them. (I have not upgraded the installation afterwards because my computer is offline!).Platform Designer Import AXI Master Component: Error: Data width must be of power of two and between 8 and 4096New Project: Logics_Suite,
