Most RecentPlatform Designer in Quartus 18.1 Standard gives the error: Error: max10_test_ddr3.mem_if_ddr3_emif_0: 'Debugging feature set' must be set to 'No Debugging' when 'Generate SOPC Builder compatible resets' is enabled.Using HLS to target the FPGA from the Host(PowerPC)what is the difference between "system view" and "standalone view" design environment views while configuring PCIe express stratix 10 IP on the platform designer?Mixed language ModelSim/Questa simulations with altera_mfModelsim 10.5b Intel FPGA licenses error,Does Quartus 18 support mega function? Can you please provide documentation? Thanks!MAX10 - Problem with booting NIOS from QSPI10AS027E3F29I2SG simulation errorVSIM HLS error due to __ihc_hls_* DPI C/C++ CallsCan't generate TB for Cyclone10GX_PCIeGen2x4_DMA_18_0_project
