Most RecentBug report: Quartus schematic to VHDL netlister produces incorrect VHDL code.pixel buffer vga in de2-115Quartus18.x issue3: if elsif errantQuartus18.x issue2: lost path to files on project reopen.I am using Simulink 2019a, what versions of DSP Builder are compatible? The table I found on the Intel website does not show 2019a.Attempting to simulate AXI3 Master BFM in Qsys system. "Library mgc_axi_master_10611 not found."Qsys now Platform designer, no error , error at same time, on wrong Avalon parameter.Intel FPGA Quartus Prime Standard 18.1 Update 1 problemModelsim: Module 'xyz' does not have a timeunit/timeprecision specification ..Got CL_INVALID_BINARY error when emulated HelloWorld example on Windows
