Most RecentHDMI RX IP questionHDMI compliance issueIn the Low Latency 100G Ethernet Intel®Stratix® 10 FPGA IP Core, can one of the two ATX PLLs be used as a clock buffer?Arria10 DMA失败Avalon -MM Intel Stratix 10 Hard IP+ for PCI ExpressWhat are some possible causes for EMIF IP for DDR4 Error "iossm_bf_cpu_cpu_test_bench/ihp_read is 'x'" during calibration for a non-HPS EMIF IP?I've instantiated a HDMI RX interface. it only can receive standard 1080P and 4K format. for a special 2K format(resolution 2560*1080), it cannot be parsed. Any different settings for this special resolution or it's just the feature?DisplayPort Source Link Training is failing sometimes. DisplayPort IP core seems to hang up.Ref Clock problem in the simple_socket_server exemple based on the Triple Speed Ethernet for Cyclone 10 GX Development kit through Quartus 18.1Debugging DisplayPort IP
