Most RecentPCIe development board with PCI express Hard IP for Stratix V crashes PC.1/2.5/5/10G Multi-rate Ethernet PHY simulation cannot reach rx_block_lockTSE IP ( discard frame during transmitting )do we have 10ge with 1GE/10GE multi-rate ethernet phy example designI am having difficulty getting the SW_RESET bit 13 of the tse_mac Command Configuration Register to work properly. It does not go from a 1 to a 0 like it should.Create a VIP Componentquartus 19.4 can not use more than 2 clocked video output II IP at one project?Triple-Speed Ethernet IP - separation of PCS&PMA from the IPGoal: 1GbE on Stratix 10 MX dev kit. With the Triple-Speed Ethernet IPcore (10/100/1000-Mbps Ethernet MAC and 1000BASE-X/SGMII PCS with Optional PMA) the GXB option is not available in Intel Stratix 10 devices. How to get this done via QSFP?Intel DisplayPort IP - DPCD Register Access
