Is the matlab model for the FFT support the block float point mode? I did not see it the matlab file
7 years ago1.6KViews0likes1Comment- 7 years ago2.7KViews0likes8Comments
How do I access the Intel® 'Cyclone V GX' DDR3 hard memory controller 'Configuration and Status Interface'?
7 years ago3.4KViews0likes8Commentswhats the purpose of CRA slave port (control and status register ) of pcie hard IP ? what is the exact usage of this port.?
7 years ago1.9KViews0likes7Comments- 7 years ago1.6KViews0likes1Comment
- 7 years ago1.7KViews0likes2Comments
- 7 years ago2KViews0likes3Comments
Why there's no clock on afi_clk output of the Hard DDR3 Memory Controller, although clock on pll_ref_clk input is present?
7 years ago2.4KViews0likes6Comments- 7 years ago1.7KViews0likes1Comment