Most RecentALTLVDS_RX input clock jitter mitigationConstrain DQS to memory clock for DDR memoryRouter Port NumberArria 10 transceivers speed gradeHow to Use: Single-Port Triple-Speed Ethernet and On-Board PHY Chip Reference DesignPart status informationOutput pin naming rules in sub-modules.Cyclone V - Dedicated configuration pins as GPIOs in user mode after AS configurationRemote debugMax 10 Socket
