Most RecentUsing JTAG on MAX10: SHIFT_IR reads 0x151 instead of 0x155. What does it mean?PLL phase shift does not workEmulated LVDS outputs and Quartus pin plannerLooking for an example Max-10 Quartus project with LVDS I/OWhat is Cyclone IV JTAG threshold specification and where is it fully documented ?Is there a USB library for HPS of Cyclone V SoCFPGA?Altera PLL and Altera PLL Dynamic reconfiguration : choose C-counter for two outputs simultaneously.Is the Max ii capable of TMDS(HDMI) output? Or would I need to move into FPGA territory do this? If you know for specifically the EPM240T100C5N even better. And any idea on resolution I could expect?How to set watchdog value for reconfiguration of MAX10?After watchdog for dual-config is enabled, the FPGA seems like not work properly every dozens of seconds. Why?
