New ContributorI'm looking for an example Max-10 Quartus project that uses LVDS I/O. I do not need SERDES. I plan to run the LVDS pins at 100MHz clock rate. I plan to use Verilog source code. Thanks,
Frequent ContributorHello there ,
sorry for late response ;
Hope you might already get some example , if not just curious , did you get chance to check in intel fpga cloud.
https://fpgacloud.intel.com/devstore/platform/?acds_version=any&family=max-10
Thank you ,
Regards,
Sree
New ContributorThere is nothing there for LVDS on the Max 10. Are there any other sources of example code for an LVDS Receiver SERDES on the Max10?
