Most RecentI have a design using EP4CE15F23C9L which has 1.2 V connected to VCCINT (core voltage) instead of 1.0 V. This design is in production and has been operational for almost 10 years. I am wondering what kind of problems/effects this will have.I have required an Intel DSP board which support Intel MKL library and programming language is C. Along with that our requirement is 16 bit ADC and DAC with sampling frequency is in Mega sampleWhat kind of file for passive parallel load of Cyclone 10?What's the reason of “Write per-bit deskew fail” during DDR4 calibrationI am working with Cyclone V. the revision name.sdc file is not created in the project folder.So how can i create thatHello, community, what is the correct pinning of the 10CX085YU484 FPGA. The 10CX085.OLB schematic symbol from Intel shows a difference at pin H2, J1 , K2 and K3 in comparison to the Device Pin-Out-File 10cx085.xls. Is the .OLB file just obsolete?Hi all, I can't find a manual that explains step-by-step how to use "4SGX230 Triple Speed Ethernet" design example. Does this manual exist? Thanks.Cyclone10 GX development kit USB 2.0 packet corruptionHey there, is it correct, that Pin AA2 , Y9, V11 and T12 at the 10CX085YU484 FPGA have only an N- and not an P-Signal at the LVDS differential channel?Programming flash from Arria 10 fabric
