ContributionsMost RecentMost LikesSolutionsRe: Quartus Fitter Random Failing Thanks for the feedback. I will try efforts other than the Performance option. Timing is not critical in this design. Re: Quartus Fitter Random Failing Thanks for the feedback here. I have VHDL parameters at the most top level file, and that is where I set the version number of the project. What I have found is that when I sometime even just change a top level parameter, the fitter will fail, while it succeeded before. So essentially it's the same design, unless you want to say that the value of register should change the fitter results. That is why I am confused at the results here. What I have also found is that at 92% the fitter fails consistently. Re: Quartus Fitter Random Failing The device is 90% full - a Cyclone VE 5CEFA7 part. I am using Quartus 20.1 lite *and* prime standard to compile, and get the same results. Quartus Fitter Random Failing I have a design for Cyclone VE that is about 90% full, and if I recompile the same design several times in a row, the design will intermittently fail on routing. The router settings have been at Performance (High Effort) and the design compiles often. Any suggestions here are appreciated. Thanks. James SolvedRe: Update single mif among multiple mif's in design with quartus_cdb It also appears that this question was asked previously here in March 2019: https://community.intel.com/t5/Programmable-Devices/Is-it-possible-to-update-one-mif-file-instead-of-the-all-set-to/m-p/694582 From the Quartus GUI, it does not appear that this is possible. However, upon further searching, it appears possible with a Makefile, as shown here: https://github.com/tomverbeure/fpga_quick_ram_update/blob/179837c409beaad14c12c24f1323ec0cfa0468f5/quartus_max10_deca/Makefile The makefile shows iterative update of all the Makefiles in a design, but one could select a limited set of makefiles to update. Re: Quartus allows redundant overloaded functions in VHDL without a compiler error ?? Nurina, Thanks for the feedback. Regarding the feedback here, is it true that the engineering team will be addressing the VHDL function overloading issue with the Pro Edition, or a general list of issues/bugs that does not include the overloading issue? Thanks, James Re: Update single mif among multiple mif's in design with quartus_cdb Thanks for the response, but it appears Quartus can only update all the MIF files in a design. Quartus cannot update a single MIF when multiple MIF's exist for a design. Thanks, James Re: Quartus allows redundant overloaded functions in VHDL without a compiler error ?? Nurina, Thanks for the feedback. I have a large codebase that I inherited with these issues, with this function scattered through out the code base. If there is some sort of fix, it would be most valuable to a current design effort. Also if the engineering team needs anything from me just let me know. Thanks. James Re: Quartus allows redundant overloaded functions in VHDL without a compiler error ?? Thanks for the feedback Nurina. Will look for future updates. James Re: Quartus allows redundant overloaded functions in VHDL without a compiler error ?? Nurina, The basic_data_types.vhd file is included in github now. The design takes approximately 10 minutes to compile. Also, if you want to see the uart readout, you need to add a small FTDI usb uart to the gpio pins GPIO_9 (Rx) and GPIO_11 (Tx) Thanks, James