AWu6
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Re: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
Hi Simon, not fix 200 BogoMIPS issue, i can't get any more help about this issue, and i have checked PLL configuration, it's configured as 800MHz main clock frequency. for slow boot issue, i think it may be related to your boot media speed, such as NAND FLASH or QSPI FLASH. i have encountered it, root cause is low speed configure of NAND FLASH controller. best regards alex5.3KViews0likes5CommentsRe: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
Hi El, btw, i want boot dual core for SMP and the kernel configured as SMP, but only one core booted, so i want to know how to boot dual core for SMP? is there any thing need configured in preloader or uboot? best regards alex5.4KViews0likes0CommentsRe: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
Hi El, this is linux booting info: NAND read: device 0 offset 0x180000, size 0x80000 524288 bytes read: OK ## Starting application at 0x3FF5A5A4 ... ## Application terminated, rc = 0x0 ## Flattened Device Tree blob at 00a00000 Booting using the fdt blob at 0x00a00000 Loading Device Tree to 03ff7000, end 03fffe5d ... OK Starting kernel ... [ 0.000000] Booting Linux on physical CPU 0x0 [ 0.000000] Linux version 4.14.73-ltsi (root@localhost.localdomain) (gcc version 4.9.4 20151028 (prerelease) (Linaro GCC 4.9-2016.02)) #16 SMP Sun Feb 16 23:03:21 CST 2020 [ 0.000000] CPU: ARMv7 Processor [413fc090] revision 0 (ARMv7), cr=10c5387d [ 0.000000] CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction cache [ 0.000000] OF: fdt: Machine model: Altera SOCFPGA Cyclone V [ 0.000000] Memory policy: Data cache writealloc [ 0.000000] percpu: Embedded 44 pages/cpu @ddbcd000 s150720 r8192 d21312 u180224 [ 0.000000] Built 1 zonelists, mobility grouping on. Total pages: 121920 [ 0.000000] Kernel command line: console=ttyS0,115200 root=/dev/mtdblock6 rw rootfstype=jffs2 init=/init mem=480M log_buf_len=1048576 [ 0.000000] PID hash table entries: 2048 (order: 1, 8192 bytes) [ 0.000000] Dentry cache hash table entries: 65536 (order: 6, 262144 bytes) [ 0.000000] Inode-cache hash table entries: 32768 (order: 5, 131072 bytes) [ 0.000000] Memory: 472776K/491520K available (8192K kernel code, 532K rwdata, 1628K rodata, 1024K init, 1158K bss, 18744K reserved, 0K cma-reserved, 0K highmem) [ 0.000000] Virtual kernel memory layout: [ 0.000000] vector : 0xffff0000 - 0xffff1000 ( 4 kB) [ 0.000000] fixmap : 0xffc00000 - 0xfff00000 (3072 kB) [ 0.000000] vmalloc : 0xde800000 - 0xff800000 ( 528 MB) [ 0.000000] lowmem : 0xc0000000 - 0xde000000 ( 480 MB) [ 0.000000] pkmap : 0xbfe00000 - 0xc0000000 ( 2 MB) [ 0.000000] modules : 0xbf000000 - 0xbfe00000 ( 14 MB) [ 0.000000] .text : 0xc0008000 - 0xc0900000 (9184 kB) [ 0.000000] .init : 0xc0c00000 - 0xc0d00000 (1024 kB) [ 0.000000] .data : 0xc0d00000 - 0xc0d85358 ( 533 kB) [ 0.000000] .bss : 0xc0d8ba3c - 0xc0ead4d0 (1159 kB) [ 0.000000] SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=2, Nodes=1 [ 0.000000] ftrace: allocating 26827 entries in 79 pages [ 0.000000] Hierarchical RCU implementation. [ 0.000000] RCU event tracing is enabled. [ 0.000000] NR_IRQS: 16, nr_irqs: 16, preallocated irqs: 16 [ 0.000000] L2C-310 erratum 769419 enabled [ 0.000000] L2C-310 enabling early BRESP for Cortex-A9 [ 0.000000] L2C-310 full line of zeros enabled for Cortex-A9 [ 0.000000] L2C-310 dynamic clock gating enabled, standby mode enabled [ 0.000000] L2C-310 cache controller enabled, 8 ways, 512 kB [ 0.000000] L2C-310: CACHE_ID 0x410030c9, AUX_CTRL 0x46060001 [ 0.000000] clocksource: timer: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604467 ns [ 0.000006] sched_clock: 32 bits at 100MHz, resolution 10ns, wraps every 21474836475ns [ 0.000019] Switching to timer-based delay loop, resolution 10ns [ 0.000247] GIC: PPI13 is secure or misconfigured [ 0.000280] GIC: PPI13 is secure or misconfigured [ 0.000442] Console: colour dummy device 80x30 [ 0.000469] Calibrating delay loop (skipped), value calculated using timer frequency.. 200.00 BogoMIPS (lpj=1000000) [ 0.000484] pid_max: default: 32768 minimum: 301 [ 0.000603] Mount-cache hash table entries: 1024 (order: 0, 4096 bytes) [ 0.000614] Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes) [ 0.001141] CPU: Testing write buffer coherency: ok [ 0.001361] CPU0: thread -1, cpu 0, socket 0, mpidr 80000000 [ 0.001660] Setting up static identity map for 0x100000 - 0x100060 [ 0.001779] Hierarchical SRCU implementation. [ 0.002273] smp: Bringing up secondary CPUs ... [ 0.002692] smp: Brought up 1 node, 1 CPU [ 0.002705] SMP: Total of 1 processors activated (200.00 BogoMIPS). [ 0.002713] CPU: All CPU(s) started in SVC mode. [ 0.003474] devtmpfs: initialized [ 0.008026] random: get_random_u32 called from bucket_table_alloc+0xfc/0x250 with crng_init=0 [ 0.008300] VFP support v0.3: implementor 41 architecture 3 part 30 variant 9 rev 4 [ 0.008502] clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns [ 0.008521] futex hash table entries: 512 (order: 3, 32768 bytes) [ 0.857848] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0xdc [ 0.864180] nand: Micron MT29F4G08ABADAWP [ 0.868223] nand: 512 MiB, SLC, erase size: 128 KiB, page size: 2048, OOB size: 64 [ 0.877649] Bad block table found at page 262080, version 0x01 [ 0.884655] Bad block table found at page 262016, version 0x01 [ 0.891826] 8 ofpart partitions found on MTD device denali-nand [ 0.897748] Creating 8 MTD partitions on "denali-nand": [ 0.902956] 0x000000000000-0x000000080000 : "NAND Flash Boot Area 512KB" [ 0.910558] 0x000000080000-0x000000100000 : "NAND Flash u-boot 512KB" [ 0.918177] 0x000000100000-0x000000180000 : "NAND Flash u-boot parameters 512KB" [ 0.926673] 0x000000180000-0x000000200000 : "NAND Flash FDT 512 KB" [ 0.933932] 0x000000200000-0x000000e00000 : "NAND Flash fpga config rbf file 12 MB" [ 0.942726] 0x000000e00000-0x000001400000 : "NAND Flash kernel 6 MB" [ 0.950306] 0x000001400000-0x000011400000 : "NAND Flash ubi rootfs 224 MB" [ 0.959677] 0x000011400000-0x000011e00000 : "NAND Flash baremetal image 10 MB" [ 0.968323] cadence-qspi ff705000.flash: couldn't determine fifo-depth [ 0.974830] cadence-qspi ff705000.flash: Cannot get mandatory OF data.5.4KViews0likes7CommentsRe: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
Hi El, boot info as below: U-Boot SPL 2013.01.01 (Dec 04 2019 - 18:04:45) BOARD : Altera SOCFPGA Cyclone V Board ------current cpu : 0 ------ CLOCK: EOSC1 clock 25000 KHz CLOCK: EOSC2 clock 25000 KHz CLOCK: F2S_SDR_REF clock 0 KHz CLOCK: F2S_PER_REF clock 0 KHz CLOCK: MPU clock 800 MHz CLOCK: DDR clock 400 MHz CLOCK: UART clock 100000 KHz CLOCK: MMC clock 3125 KHz CLOCK: QSPI clock 400000 KHz RESET: WARM SDRAM: Initializing MMR registers SDRAM: Calibrating PHY SEQ.C: Preparing to start memory calibration SEQ.C: CALIBRATION PASSED SDRAM: 1024 MiB NAND: Denali NAND controller U-Boot 2013.01.01 (Dec 04 2019 - 18:07:52) CPU : Altera SOCFPGA Platform BOARD : Altera SOCFPGA Cyclone V Board I2C: ready DRAM: 1 GiB NAND: NAND: Denali NAND controller 512 MiB MMC: ALTERA DWMMC: 0 In: serial Out: serial Err: serial Net: mii0 Hit any key to stop autoboot: 0 printer-loader #5.4KViews0likes0CommentsRe: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
hi El, May I know the process of the Linux compilation that was made? OR is this from a prebuilt image used from Rocketboards? Which Linux/version are you using? -- not prebuilt image. compiled myself, linux version is Linux socfpga 4.14.73-ltsi, download from https://github.com/altera-opensource compiler is download from linaro Also, what was the booting method, via SD card, QSPI etc? booting from NAND FLASH. Was there any error/issue during the booting of preloader/u-boot? Can you share the boot logs for preloader,u-boot,kernel and Linux? yes, of course, i will post it later. by the way, rootfs come from the EDS installation directory.5.4KViews0likes0CommentsRe: why cyclone v soc HPS running linux can only get 200 BogoMIPS?
Sending discover... Sending discover... No lease, failing Starting portmap daemon... INIT: Entering runlevel: 5 Starting OpenBSD Secure Shell server: sshd NET: Registered protocol family 10 IPv6: ADDRCONF(NETDEV_UP): eth0: link is not ready done. Starting syslogd/klogd: done Starting Lighttpd Web Server: lighttpd. Stopping Bootlog daemon: bootlogd. Poky 8.0 (Yocto Project 1.3 Reference Distro) 1.3 socfpga_cyclone5 ttyS0 socfpga_cyclone5 login: root root@socfpga_cyclone5:~# cat /proc/cpuinfo Processor : ARMv7 Processor rev 0 (v7l) processor : 0 BogoMIPS : 1594.16 processor : 1 BogoMIPS : 1594.16 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x3 CPU part : 0xc09 CPU revision : 0 Hardware : Altera SOCFPGA Revision : 0000 Serial : 0000000000000000 root@socfpga_cyclone5:~# this is the prebuilt image from rocketboards.org, boot from SD CARD. so huge gap.5.4KViews0likes0CommentsRe: googol使用cyclone v soc，调用hwlib库中的CPU复位接口时不正常
Hi, boot from QSPI flash. right now customer are debugging software, reset is called in their main function. they called this function for CPU reset. ALT_STATUS_CODE alt_reset_cold_reset(void) { alt_write_word(ALT_RSTMGR_CTL_ADDR, ALT_RSTMGR_CTL_SWCOLDRSTREQ_SET_MSK); return ALT_E_SUCCESS; }1.1KViews0likes0Comments