gustifix2
New ContributorJoined 2 years ago
User Profile
New Contributor
User Widgets
Contributions
Re: OneAPI for Agilex 7 I-Series Dev Kit: aocl diagnose acl0 and board_test sample fail
Hello, I couldn't really narrow down the cause of the error and I'm not sure the OpenCL runtime code is the right place to look. Do you have any recommendations how to proceed from here? Thanks and best regards! FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera, I just created a new post because the current issue isn't really related to the original one I created this post for anymore: https://community.intel.com/t5/FPGA-SoC-And-CPLD-Boards-And/OneAPI-for-Agilex-7-I-Series-Dev-Kit-aocl-diagnose-acl0-and/m-p/1663345#M29250 Best wishes! FelixOneAPI for Agilex 7 I-Series Dev Kit: aocl diagnose acl0 and board_test sample fail
Hello! This is a follow up to my previous post. I am following the oneAPI ASP Getting Started User Guide for the Agilex 7 I-Series Development Kit (2x R-Tile, 1x F-Tile) . At step 2.5.3 Initialize Board and Run Diagnostic Test `aocl diagnose` succeeds but `aocl diagnose acl0` fails. I also tried the `board_test` sample in the next section of the guide. Both fail with the same error: /nfs/site/disks/hld_runners_2/dynamic/alxa_kress/_work/applications.fpga.oneapi.stella/applications.fpga.oneapi.stella/external/opencl-fpga-runtime/src/acl_hal_mmd.cpp:2061: void acl_hal_mmd_status_handler(int, void*, aocl_mmd_op_t, int): Assertion `status == 0' failed. As mentioned in the last post, I tried using the pre-compiled FIMs from https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2024.2-1. The default one (iseries-dk-images_ofs-2024-2-1.tar.gz) leads to the same error in step 2.5.1 that my last post was originally about. The other two (iseries-dk-1link-images_ofs-2024-2-1.tar.gz and iseries-dk-2link-images_ofs-2024-2-1.tar.gz) work but also fail `aocl diagnose acl0` and `board_test` like the self-built FIM. That is why I don't think the FIM is the problem and I am investigating the other parts of the stack now. So far I tried the latest release of the OPAE SDK (2.14.0-1) and the latest commit of linux-dfl-backport instead of the versions mentioned in the guide. This did not change anything about the errors. Next I'll take a closer look at the OpenCL runtime source code where the error message stems from (acl_hal_mmd_status_handler) and try debugging the `board_test` and other oneAPI samples with GDB to narrow down where in the software stack the problem occurs. I will post an update as soon as I find anything new, but I'd appreciate it if you could help me already with the information provided so far. Thanks! I also attached the output of `aocl diagnose` and `board_test`. Best regards! FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera, No worries, thanks! I'll try some debugging in the meantime. I saw that a prebuilt FIM is available at https://github.com/OFS/ofs-agx7-pcie-attach/releases/tag/ofs-2024.2-1, so I'll follow the guide again using this FIM. If this doesn't change anything, I will also investigate the error in the board_test sample more. Maybe I can find out where in the stack the problem occurs. Best wishes! FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera, For the board_test sample only 3 of the 7 tests pass, 2 (kernel clock frequency), 4 (kernel latency measurement), and 7 (unified shared memory bandwidth). I attached the full output. Edit: I just saw that test 7 is actually skipped because the board does not support USM, so only 2 and 4 passed. I also noticed the following error that continually appears in dmesg: [ +0.000126] pcieport 0000:00:01.0: AER: Correctable error message received from 0000:00:01.0 [ +0.000002] pcieport 0000:00:01.0: PCIe Bus Error: severity=Correctable, type=Physical Layer, (Receiver ID) [ +0.000001] pcieport 0000:00:01.0: device [8086:a70d] error status/mask=00000001/00002000 [ +0.000000] pcieport 0000:00:01.0: [ 0] RxErr (First) The BTS looks fine. I attached pictures of the 3 memory tests as examples. Thanks and best wishes! FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera, Thank you for all the help so far! With the new build_top.sh command the compile succeeded. I continued the guide until section 2.5.3, where aocl diagnose succeeds but aocl diagnose acl0 fails. I attached the output of both commands. I will try compiling the original FIM without my modifications to the DDR config again but use the new build_top.sh command and report back if it changes anything. Best wishes FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera, After removing the 2 "North I/O Row" interfaces as described previously and removing all _mem[2] and _mem[3] constraints from syn/board/iseries-dk/setup/emif_loc.tcl, the FIM compile succeeded without timing violations after a few tries with different seeds. However, after repeating the steps with OPAE_PLATFORM_ROOT now pointing to this new FIM build's pr_build_template directory, I got the same error (attached txt file) as in the beginning at step 2.5.1 Compile Initialization Bitstreams. Best wishes! FelixRe: OneAPI for Agilex 7 I-Series Dev Kit: build-default-binaries.sh fails
Hi @BoonBengT_Altera , Could you point me to some documentation for what exactly should be changed? I assume I have to change the memory configuration of the FIM, similar to 4.7 Modify the Memory Sub-system. I tried removing the 2 DDR4 interfaces with location "North I/O Row" in the picture below: I assume the "North I/O Row" is connected to the two DIMM slots and "South I/O Row" to the 2x8GB soldered to the board based on this picture: However, with just two "south" interfaces and after removing unused signals in the "Interface Requirements" window, I get a compilation error in build_top.sh script about the fitter not being able to place pins. It looks like I also have to adjust the pin constraints and remove the now unused pins. However, I'm not sure if this is even the right approach to change the RAM configuration to 2x8GB, so I wanted to ask here again first. Also, I will be on vacation for two weeks and continue to work on this afterwards. Thanks and best wishes! Felix
