CS72
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new "no-cost license" 24.1 announced - latest Lite being 23.1 on download page
Hi, saw this announcement yesterday for 24.1: Intel® Quartus® Prime Pro Edition Design Software Version 24.1 B115 for Windows stating " Design with Agilex™ 5 FPGA E- Series with a no-cost license in Quartus Prime Pro 24.1. " on donwload page latest Lite is 23.1 - just confused, what is meant by "no-cot license" statement... Is it a 24.1 Prime no-cost license limited to the Agilex 5 ?Re: is there the same silicon chip used in different housings
Hi, here is a screenshot of a comparison between the both *.pof files - they differ not only in the first lines including the device name, but also all through the imho configuration data... While the original file is dated 2007 a recompilation with current machine gives identical file, i.e., the difference seems not to be related to the machine but the fitting algorithm being different? KR, CarlhermannRe: is there the same silicon chip used in different housings
Hi, for sure this idea is very strange, as it requires a custom made PCB to interconnect the BGA Pins with the QFP pads on the existing hardware. Something you would not think of in "normal" designs 😉 But a redesign of the hardware for direct assembly of the BGA is no option, being high-effort, ... of a proven in use design. The "normal an intended" way is using the vertical migration feature, supporting different logic sizes being placed on same PCB, depending on the application's need. In this special case, the problem is a combination of obsolescence and need to support old hardware. The original used FLEX10K is a 10K100ARI, i.e., a RQFP240 pin device. Being obsolete for many years now, we are meanwhile also running out of stock at Brookers. The 10K100 has been offered in the 484BGA (10K100AFI). To keep credits from the many years proven in use design, we would also like to re-use the programming file as is. If the chip "inside" in the different housings (RQFP and BGA) is the same silicon, with just more or less I/O cells being bonded to I/O pins (depending on the housing), the original programming file should configure the BGA packed chip as well, shouldn't it? (The silicon is not aware of the housing used...) With the cross-reference between RQFP Pin to BGA Pin, the adapter board should be designed to connect the correct pins and thus, the BGA on the adapter should be identical to the original RQFP housed device w/o any change of the programming file imho... To prove this idea, I created a reference using the BDSL files, using the Boundary Scan Cell information section. RQFP Pin6 = BGA Pin C22 ... Changing the target device and updating the pin-assigments accordingly, the *.pof is different... Using a HexEditor to open the *.pof this is shown in the target device being part of the datastream, originally the ARI240, noe the AFI484. If this is not part of the "real" configuration data for the chip ("just" information showing up in the programmer window?), this mismatch when using the original *.pof with the BGA should not prevent configuration and with the correct PCB between the original HW and the BGA housing the "ARI240 targeting" POF should be fine, shouldn't it? Many thanks taking time to support this strange issue 🙂 KRRe: is there the same silicon chip used in different housings
Hi, this is the extract from the pgm_parts.txt file from Quartus 9.0 for the device: EPF10K100A 88 20 18 15 0 EPF10K100A 0 0 10 0 1 0x001000DD 0xFFFFFFFF 0 155/000 0 EPF10K100AB356 88 20 18 1 356 EPF10K100A 0 0 10 0 1 0x001000DD 0xFFFFFFFF 0 155/000 0 EPF10K100AB600 88 20 18 1 600 EPF10K100A 0 0 10 0 1 0x001000DD 0xFFFFFFFF 0 155/000 0 EPF10K100AF484 88 20 18 4 484 EPF10K100A 0 0 10 0 1 0x001000DD 0xFFFFFFFF 0 155/000 0 EPF10K100AR240 88 20 18 12 240 EPF10K100A 0 0 10 0 1 0x001000DD 0xFFFFFFFF 0 155/000 0 I assume the 0x001000DD is the device ID, i.e. identical for all housings... The POF on the other hand includes in the header complete device ID (with housing and speed grade). The two devices are in detail the (currently used) EPF10K100ARI240-3 and the (intended) EPF10K100AFI484-3.Re: Modelsim 10.5 error on gate level sim: Fatal: SDF files require Intel FPGA Edition primitive library
Hi, I meanwhile installed the QII7.1 WebEdition (found the old CD) and unfortunately even the packed free ModelSim 6.1g requires a license... As expected, this license cannot be retrieved via the self service license center (SSLC) for being "too old"... Thus, where to get a valid license?
