ContributionsMost RecentMost LikesSolutionsAvalon MM slave component: readdata signal is always zero I have this simple Avalon MM slave component where I set avs_s0_readdata to a constant value: But avs_s0_readdata always stays with value zero. I've tried to achieve this in three different ways, showed in the code commented. Look at this signal tap logic analizer: readdata is always 0h, even when read signal is enabled. Shouldn't readdata be always the constant value I set in the component's code? Re: [Noob DE10-nano] Can I deploy a generic rbf from linux using Cyclone V SoC? Hi, First of all, thank you zangman for the tutorial you've built on the DE10-Nano, it has been helpful in my journey! I am running the SD Card Image for Azure IoT (ubuntu 18.04 LXDE) taken from Terasic's website on my DE10-Nano. (I'll explain my use case with this linux image, but I believe the same would apply for any linux image that runs a GUI, such as the other LXDE ones provided in Terasic's website) While ubuntu LXDE is running in the DE10-Nano's HPS, I'm able to flash a new design on the FPGA via USB-Blaster II using Quartus programmer tool runnin on my laptop. When doing this, the DE10-Nano's HDMI output stops sending signal and the monitor screen connected to it goes blank (as expected, since the hardware design which I flashed the FPGA with does not have what is needed for the HDMI output coming from the HPS to work). However, the ubuntu system continues to work, as I can still use UART serial terminal (USB connected to my laptop) and navigate the system normally; I jost lose the GUI. I understand that the SD Card Image for Azure IoT (as well any other LXDE image) has a .rbf file that is automatically flashed on the FPGA when the system boots, and that this .rbf file has what is needed for the HPS HDMI output to work and be able to see the LXDE GUI on a monitor. I understand that if I want to flash a new hardware design on the FPGA using quartus and USB-Blaster II while LXDE is running on the HPS and not lose video signal, my hardware design would need to contain something specific for the HPS HDMI output to keep working. I'm not able to figure out what is this "something specific" that my hardware design needs to have in order for the HPS HDMI output to work. The SD Card Image for Azure IoT does not come with the hardware design source, only in its binary form, so I can't study it to try to understand what HDL/Qsys module(s) enables the HDMI output to come from the HPS. The only hint I've found on the internet is that a Frame Buffer might be a part of the solution, but I can't figure out the rest. Do you or anyone else have any ideas what the hardware design needs to have in order for the HDMI output from the HPS to work? Thanks in advance, I don't know where else to find help and I'm trying to tackle this problem on my own for a long time now.