ContributionsMost RecentMost LikesSolutionsRe: ARRRIA II .JIC or .RPD encryption yes Re: SPI (3 Wire Serial) without MISO thanks! SPI (3 Wire Serial) without MISO hi, it's possible to use the SPI (3 Wire Serial) IP CORE (Arria2) without connecting a signal to the MISO port? if so, should I connect it to a '1' default or '0'? thanks ARRRIA II .JIC or .RPD encryption Hi, I'm trying without success to generate a .JIC or .RPD encrypted file for Arria II. so far, I successfully generated an .epk file but wasn't able to "implemented" it to a .JIC or .RPD. please help Re: generate ekp file for arria 10 GX device hi, I have the same problem. I'm trying to generate an encrypted .JIC file. I was able to generate the .epk file (I have a Quartus license) BTW, I'm using Arria2 Re: max10 internal memory write protection obviously it's the first thing I checked... not helpful max10 internal memory write protection hi, I'm using the max10 FPGA (with quartus prime lite 18.1) how can I check if it's configured to internal memory write protection (and change it if not)? Re: keeping signals for signaltap some internal signals in my project (flag, counter, etc) Re: keeping signals for signaltap I tried the "keep" and/or "preserve" (I always look for pre-synthesis) and doesn't work.. keeping signals for signaltap Hi, I'm using Quartus prime lite edition (language VHDL). how can I "keep" signals so they appear in the siganltap search? Solved
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