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Re: EMMC daughter board for Arria 10 GX FPGA Development Kit
Hi Farabi, I knew eMMC was supported by Arria 10 SoC HPS part. What I'm trying here is demo the EMMC controller in FPGA part not using HPS part so it is possible with Arria 10GX board. I want to check what type of EMMC daughter board connector can I use to design the custom daughter board.1.3KViews0likes0CommentsRe: Analyze HDL file encrypt_1735
I have successfully Run Analysis & Synthesis file dti_phy_ctl_blk.vp But I want to create components from my design so I use Platform Design -------- I use Platform Design to create new components 1. I add dti_phy_ctl_blk.vp 2. Set type Verilog HDL 3. Set Attributes is Top-Level file 4. Run Analyze HDL Files Then I got that error Error: Internal Sub-system: QIS, File: /quartus/synth/qis/qis_rtl_stage_utility.cpp, Line: 705 Error: No modules found when analyzing [PATH]/dti_phy_ctl_blk.vp. How can I finish creating a new component.1.6KViews0likes0CommentsCan not open board test system
Hi, I'm using Quartus 22.3 and Intel Arria 10 GX kit. When I open Board test system, it has two errors 1. SEVERE: java.io.IOException: Cannot run program "/tools/intelFPGA/22.3/quartus/sopc_builder/bin/system-console": error=2, No such file or directory Oct 13, 2022 3:26:38 PM com.altera.bts.BtsView <init> I found this file in /tools/intelFPGA/22.3/syscon/bin/system-console and copy to the missing path 2. INFO: Board version: Rev E3, chip version: PRD Oct 13, 2022 3:45:08 PM com.altera.bts.systemconsole.client.ClientApp attachServer INFO: [/tools/intelFPGA/22.3/quartus/sopc_builder/bin/system-console, --server] Oct 13, 2022 3:45:08 PM com.altera.bts.systemconsole.client.ClientApp attachServer INFO: Here is the standard output of the command: Oct 13, 2022 3:45:10 PM com.altera.bts.BtsView <init> SEVERE: java.io.IOException: ServerPort 65536 is not a valid TCP port. Can you help how to fix this issue?Solved1.2KViews0likes3CommentsAnalyze HDL file encrypt_1735
I encrypted the hdl file with encrypt_1735 (dti_phy_ctl_blk.v -> dti_phy_ctl_blk.vp) "encrypt_1735 dti_phy_ctl_blk.v --language=verilog --quartus" then I took that file to analyze and got an error: Error: Internal Sub-system: QIS, File: /quartus/synth/qis/qis_rtl_stage_utility.cpp, Line: 705 Error: No modules found when analyzing [PATH]/dti_phy_ctl_blk.vp. How can I synthesize encrypted files? Thanks and best regards phuongnn01.7KViews0likes7Comments