SivaKona
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Re: Read responses on not reaching PIO interface through mm_interconnect
Hi Wincent_Intel, Good Morning! We have generated an SOF with Quartus Version 22.3 and observed the same behavior to persist. The issue is NOT resolved yet. Request you for further inputs. Is this behavior due to issues in mm_interconnect or PCIe Endpoint? Regards Siva Kona1.5KViews0likes0CommentsRead responses on not reaching PIO interface through mm_interconnect
Hi, Quartus Version : 22.2.0.94 A "Multi Channel DMA Intel® FPGA IP for PCI Express" IP is integrated with AXI4 DUT and On Chip Memory. Data Responses for BAR2 MMIO read requests are not reaching PIO interface. The attached "NoReadResponseAtPIO.png" shows => a valid Read response is present on DUT AXI interface. => rx_pio_waitrequest_i goes low => rx_pio_readdatavalid_i does not toggle. This results in a hang in mm_interconnect. Subsequent read/writes initiated on rx_pio does not pass through mm_interconnect. How can we overcome this issue? Regards Siva Kona1.6KViews0likes3CommentsRe: How to find the number of outstanding requests supported by mm_interconnect
Parameters below control the Max outstanding transaction support on the Host interfaces. set_interface_property altera_axi4_master3 readIssuingCapability 1 set_interface_property altera_axi4_master3 writeIssuingCapability 1 set_interface_property altera_axi4_master3 combinedIssuingCapability 11.1KViews0likes0CommentsRe: Stratix 10 GX EMIF IP corrupting Host Boot code
Hi Adzim, Following are the EMIF Interface Configuration steps that we followed. Instantiate “External Memory Interfaces Intel Stratix 10 FPGA IP” from “Memory Interfaces and Controllers” library of IP Catalog Applied “Stratix 10 GX H-Tile FPGA Development kit with DDR4 HiLo” Preset as shown in Snapshot “preset_cfg_changes_1.png” Exported pll_ref_clk with name ddr_ref_clk Specified connection from “rxm_bar0” of PCIe EP instance to “ctrl_amm_0” of “emif_s10_0” instance. And Tool identified two Errors Error: gyann_fpga.emif_s10_0.ctrl_amm_0: Data width must be of power of two and between 8 and 4096 To overcome the Error, we switched to Controller Tab and set “Enable Error detection and Correction Logic with ECC” in “Configuration, status and Error handling” sub tab. This setting changed the Avalon amm Data width from 576 to 512 Data corruption Warning Warning: gyann_fpga.pcie_s10_hip_avmm_bridge_0.rxm_bar0/emif_s10_0.ctrl_amm_0: emif_s10_0.ctrl_amm_0 does not have byteenables. Writes from narrow master pcie_s10_hip_avmm_bridge_0.rxm_bar0 may result in data corruption To overcome the Warning, we switched to “Memory” Tab, to reset “Write DBI” and set “Data mask” in “Topology” sub tab Setting Data mask along with “Write DBI” threw Errors No timing violations are seen in the Build reports. We have not tested the EMIF IP standalone, We are working to try that after your suggestion. We have captured videos of Successful reboot and failed reboot scenarios. During the failure, The Host just Shuts down and does not Power up at all. I will share the videos if required over email. Regards Siva Kona2KViews0likes0CommentsRe: pcie gen3x8 DMA EndPoint with HPTXS path is not meeting timing
I realized that the longer IC (Inter Connection) delays are due to the paths to farther Block RAMS blocks. When I reduced OnChip memory size from 16MB to 2MB , The design met Setup time. Is there a way close timing without reducing the Block RAM usage? Regards Siva Kona2KViews0likes0Comments