nikhl
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Re: Failed Co simulation of a Example HLS design
Hi @hareesh , No , the problem has not solved, I think it is because of the missing 32 bit arch libraries. I was unable to find few of the libraries mentioned in getting started guide of intel HLS for my ubuntu 18.04. Can you suggest where I can get those libraries.Failed Co simulation of a Example HLS design
Hi , I am have installed the intel Quartus prime 22.2 development suite in my system and tried to compile and test the HLS counter example design but it fails in the Co-simulation. i++ counter.cpp -v -march=Arria10 -o test-fpga Target FPGA part name: 10AX115U1F45I1SG Target FPGA family name: Arria10 Target FPGA speed grade: -1 Analyzing counter.cpp for testbench generation Creating x86-64 testbench Analyzing counter.cpp for hardware generation Verifying version information in the included files. Expecting version 22.2.0.46.1 for all included files. Included files passed version check. Checked: none. Optimizing component(s) and generating Verilog files Generating cosimulation support Generating simulation files for components: count HLS simulation directory: /home/lsai_nikhil/intelFPGA_pro/22.2/hls/examples/counter/test-fpga.prj/verification. HLS Elaborate verification testbench FAILED. See /home/lsai_nikhil/intelFPGA_pro/22.2/hls/examples/counter/test-fpga.prj/debug.log for details. Error: Cosim testbench elaboration failed. Makefile:53: recipe for target 't I have checked the debug .log , Debug log output: /home/lsai_nikhil/intelFPGA_pro/22.2/hls/host/linux64/lib/libhls_cosim_msim32 # -dpioutoftheblue 1 -sv_lib /home/lsai_nikhil/intelFPGA_pro/22.2/hls/host/linux64/lib/libhls_cosim_msim32 # [exec] elab # vsim -dpioutoftheblue 1 -sv_lib /home/lsai_nikhil/intelFPGA_pro/22.2/hls/host/linux64/lib/libhls_cosim_msim32 -L work -L work_lib -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_v er -L twentynm_ver -L twentynm_hssi_ver -L twentynm_hip_ver -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L twentynm -L twentynm_hssi -L twentynm_hip -L hls_sim_main_dpi_controller_10 -L main_dp i_controller -L hls_sim_component_dpi_controller_10 -L dpic_count -L avalon_conduit_fanout_10 -L count_cfan -L count_en_cfan -L hls_sim_clock_reset_10 -L clock_reset -L avalon_concatenate_singlebit_condui ts_10 -L cat_done -L count_internal_10 -L count -L cat_cwfsw -L avalon_split_multibit_conduit_10 -L sp_cstart -L altera_irq_mapper_2000 -L tb tb.tb # Start time: 10:26:00 on Oct 19,2022 # ** Fatal: ** Fatal: (vsim-3827) Could not compile 'export_tramp.so': cmd = '/home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/gcc -shared -fPIC -m32 -B/usr/lib32 -g -I. -I"/home/lsai_nikhil/intelFPGA_pro /19.3/modelsim_ase/include" -I"/home/lsai_nikhil/intelFPGA_pro/19.3/modelsim_ase/../oem/include" -o "/tmp/lsai_nikhil@server1_dpi_11933/linuxpe_gcc-9.3.0/export_tramp.so" "/tmp/lsai_nikhil@server1_dpi_119 33/linuxpe_gcc-9.3.0/export_tramp.S"' # (vsim-50) A call to system(/home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/gcc -shared -fPIC -m32 -B/usr/lib32 -g -I. -I"/home/lsai_nikhil/intelFPGA_pro/19.3/modelsim_ase/include" -I"/home/lsai_nikhil/ intelFPGA_pro/19.3/modelsim_ase/../oem/include" -o "/tmp/lsai_nikhil@server1_dpi_11933/linuxpe_gcc-9.3.0/export_tramp.so" "/tmp/lsai_nikhil@server1_dpi_11933/linuxpe_gcc-9.3.0/export_tramp.S" >'/tmp/quest atmp.j5QHxs' 2>&1) returned error code '1'. # The logfile contains the following messages: # /home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/../lib/gcc/x86_64-pc-linux-gnu/9.3.0/../../../../x86_64-pc-linux-gnu/bin/ld: skipping incompatible /home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/../lib/gcc/x8 6_64-pc-linux-gnu/9.3.0/libgcc.a when searching for -lgcc # /home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/../lib/gcc/x86_64-pc-linux-gnu/9.3.0/../../../../x86_64-pc-linux-gnu/bin/ld: cannot find -lgcc # /home/lsai_nikhil/intelFPGA_pro/22.2/gcc/bin/../lib/gcc/x86_64-pc-linux-gnu/9.3.0/../../../../x86_64-pc-linux-gnu/bin/ld: cannot find -lgcc_s # collect2: error: ld returned 1 exit status # # No such file or directory. (errno = ENOENT) # # # FATAL ERROR while loading design # ** Error: Error loading design # Executing ONERROR command at macro ./msim_compile.tcl line 15 # End time: 10:26:15 on Oct 19,2022, Elapsed time: 0:00:15 Can anyone help me to resolve the issue? @intelRe: "Found more than one suitable slot" while testing the 10GBE PAC-PAC test
Hi, I have uncommented those lines the host code. It is giving the "found more than one suitable slot" again. Also while i am executing using this command "./pac_hssi_e10 -b AF --channel=0 --action=stat" , it is showing invalid bus. server2@server2:~/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/eth_e2e_e10/sw$ ./pac_hssi_e10 -b AF --channel=0 --action=stat invalid bus: AF ./pac_hssi_e10 PAC HSSI configuration utility Usage: pac_hssi_e10 [-h] [-b <bus>] [-d <device>] [-f <function>] [-s Src. MAC] [-m Dest. MAC] [-p Number of packets] [-l Packet length] -a action -h,--help Print this help -b,--bus Set target bus number -d,--device Set target device number -f,--function Set target function number -c,--channel Set HSSI channel (0 - ffffffff) -s,--src_mac Set Source MAC (in the format AA:BB:CC:DD:EE:FF) -m,--dest_mac Set Destination MAC (in the format AA:BB:CC:DD:EE:FF) -p,--packets Total number of packets (in hex format e.g. 0x100) -l,--pkt_len Packet length bytes (in hex format e.g. 0x100) -a,--action Perform action: off Assert MAC resets on Deassert MAC resets stat Print channel statistics stat_clear Clear channel statistics loopback_enable Reset MAC, enable internal channel loopback, send packets, and print stats loopback_disable Reset MAC, disable internal channel loopback, send packets, and print stats pkt_send Send 0x10000 packets server2@server2:~/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/eth_e2e_e10/sw$ ./pac_hssi_e10 AF --channel=0 --action=stat Found more than one suitable slot, please be more specific. server2@server2:~/inteldevstack/a10_gx_pac_ias_1_2_1_pv/hw/samples/eth_e2e_e10/sw$ ./pac_hssi_e10 86 --channel=0 --action=stat Found more than one suitable slot, please be more specific.
