ihsan28
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Linux kernel source for SoC FPGA Intel
Hi, I notice that there are two sources for building a Linux kernel for SoC FPGA. First is https://github.com/altera-fpga/linux-socfpga, and the second is https://github.com/altera-fpga/gsrd-socfpga . Could anyone give an easy explanation about the differences? And when should I use one of those? Thank you.1.6KViews0likes4CommentsHPS to FPGA bridge in GSRD Agilex 7 m-series
Hi, I am following this tutorial to generate the GSRD for my fpga https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/ everything work, until I want to test the HPS to FPGA bridge. At least, the LW bridge has been used in the design for controlling the LEDs, right? but I cannot manage to find out how to access or manipulate it? Does the bridge include in the GSRD? or no? Thank you.1.7KViews0likes4CommentsAgilex 7 M-series GSRD wrong DDR5 memory size
Hi, I followed the development of GSRD for Agilex 7 M-series, like in https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-7/m-series/hbm2e/ug-gsrd-agx7m-hbm2e/ When I boot, I get init_mem_cal: Initial DDR calibration IO96B_0 succeed DDR: Calibration success io96b_mb_init: num_instance 1 io96b_mb_init: get memory interface IO96B 0 io96b_mb_init: IO96B 0 mem_interface 0: ip_type_ret: 0x1 io96b_mb_init: IO96B 0 mem_interface 0: instance_id_ret: 0x0 io96b_mb_init: IO96B 0: num_mem_interface: 0x1 DDR: Warning: DRAM size from device tree (2048 MiB) mismatch with hardware (4096 MiB). DDR5: 2048 MiB ecc_enable_status: ECC enable status: 0 DDR5: size check success DDR5: firewall init success DDR5 init success So I am thinking of changing the size of DRAM in the device tree, but I cannot find out where I should change it. Could anyone help me find out? Thank you.1.3KViews0likes3CommentsReconfigure FPGA Agilex 7 M-series without recompile Yocto Linux
Hi, We have Agilex 7 M-series. We managed to run an example of Yocto Linux on the ARM core, and based on my understanding, every time we have a new bitstream, we need to compile Yocto again and rewrite the SD card. right? So, I guess there is no Ubuntu support or ready for ARM core in Agilex 7, like in Xilinx Zynq, they have Ubuntu support. But in our FPGA, we want to find a way to reconfigure the FPGA fabric without re-burning the SD card. Is it in any way possible to do that? I noticed about configure via AVSTx8. But I am still confused about that and still doubt if that's what I need or not, because it says after reboot, it will be stuck, so there is no reboot for the ARM core. Please help me with a hint or info regarding that. Thank you very much. Best regards, Ihsan1.4KViews0likes3Comments