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dim1
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Re: Run-time errors using EMIF in Agilex 5 NIOS-V design
Hello Radu, Thank you for the detailed explanation! In the IP catalog, I see AXI Address Span Extender IP. Is the AXI Address Span Extender IP equivalent to the Address Span Extender? Would not that be better to use, considering that the EMIF so_axi4 is an AXI4 bus? Another question: In the EMIF IP User Guide, in Table 12 Limitations on Narrow Read Transfer, in the Non-Lockstep configuration, when only the primary controller is used, does it mean that narrow read is supported on all Agilex 5 D and E series devices, except on the two devices listed in the table? Thank you, D.Re: Run-time errors using EMIF in Agilex 5 NIOS-V design
Hello Radu, Thank you for your message and suggestions. I already did LPDDR4 memory test, using the Altera sample program available for NIOS II, re-built for NIOS-V. Run the application from the on-chip RAM only. All tests passed. I added second Reset Controller, as suggested. That changed nothing. Next I captured arsize and I saw that it is 2, not 5. I saw that on every instruction fetch, arsize is always 2. The mcause I was seeing are 0, 2, 4 and 6. Though, I was using NIOS-V g initially, and then switched to NIOS-V m, just to keep things as simple as possible. Finally, I add the Address Span Extender - and it worked. With it, now the application starts and runs Ok. Is using the Address Span Extender the only way to use EMIF with NIOS-V, for XIP from LPDDR4, without having to create a new IP? Thank you, D.Re: Run-time errors using EMIF in Agilex 5 NIOS-V design
I did notice that s0_axi4_ctrl_ready was not used. Attached is an updated design where the s0_axi4_ctrl_ready is connected to the NIOS-V reset, to keep NIOS-V in reset until the EMIF is ready. It did not change anything - still the same problem.Run-time errors using EMIF in Agilex 5 NIOS-V design
Hello, I am using Quartus Prime Pro 26.1.1, with the Agilex 5 development board (AXE5-Eagle). I am trying to run the NIOS-V code from the LPDDR4 memory, using JTAG to download/debug. The reset and exception vectors are set to the On-Chip RAM. I used the sample design provided for that board - AXE5 Eagle mipi_hdmi_mira220 and removed everything related to MIPI and HDMI. Added JTAG Uart IP. The resulting sample design is attached (mipi_hdmi_mira220.zip). In the software/ directory you can also see the FreeRTOS BSP I used. I created a simple FreeRTOS application that just prints some string to stdout. What I am seeing is - the RISC-V processor throws exceptions - one of the following - Misaligned Read Address, Misaligned Write Address or Invalid Instruction. This happens in alt_load_section(). If I execute step-by-step, no exception is thrown. But if I just run the application it fails. Is there something else that need to be added/updated/changed, in order to be able and execute code from LPDDR4 using the EMIF IP? I could not find any existing sample design, using NIOS-V and EMIF, with code execution from EMIF. Thank you, D.Re: LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello Liang Yu, So I tried to manually add linker memory device, following the steps in the link you provided. Unfortunately, it does not work. What happens is, a second, duplicate device is created, and still not accessible for creating linker regions, section mappings etc. Here is how the memory map looks originally. The EMIF IP is shown as lpddr4_s0_axi4: I add a new Memory Device, with name lpddr4_s0_axi4, Base Address 0 and Size 0x80000000. This results in the following Memory Map: Notice how now there are two lpddr4_s0_axi4 devices, and neither one of them is usable in the BSP Linker Script. Please advise. Thank you, D.LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
