dim1
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Re: LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello Liang Yu, So I tried to manually add linker memory device, following the steps in the link you provided. Unfortunately, it does not work. What happens is, a second, duplicate device is created, and still not accessible for creating linker regions, section mappings etc. Here is how the memory map looks originally. The EMIF IP is shown as lpddr4_s0_axi4: I add a new Memory Device, with name lpddr4_s0_axi4, Base Address 0 and Size 0x80000000. This results in the following Memory Map: Notice how now there are two lpddr4_s0_axi4 devices, and neither one of them is usable in the BSP Linker Script. Please advise. Thank you, D.LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
