Desani
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Can we drive QSFP reference clock using an internal clock generated from a PLL
While driving the reference clock(322.2 MHz) to 10G ethernet mac interface, I am prompted with the error below, Error(18957): Signal u1|iopll_0|stratix10_altera_iopll_i|outclk[0] is constrained to be routed locally to port REF_IQCLK on destination dut_inst|atx_pll_inst|xcvr_atx_pll_s10_htile_0|ct1_hssi_pma_lc_refclk_select_mux_inst, but this signal must be routed through the global network Tried using the constraint set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "u1:inst|iopll_0|stratix10_altera_iopll_i|outclk[0]" -entity altera_eth_top to make the PLL output global but still fails to compile. I am generating the ref_clk_clk using a PLL, is this not allowed? How do I resolve the issue? Any help is appreciated. Thanks RaamSystem console can't link device (Device has different visible SLD agents)
SEVERE: Device /devices/632AC0DD@1#USB-1#Intel Stratix 10 MX FPGA Development Kit does not match design altera_eth_top.sof (Device has different visible SLD agents) Getting the above error when trying to link device to the compiled sof for the Stratix 10 MX FPGA Development Kit. Any help is appreciated, Thanks
