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Re: No output from FFT IP
Dear @CheePin_C_Intel , I did not fully get the implications of using the block floating point and fixed point and the difference of the consequences of using them. I get a working and erroneous implementation by using the fixed point variable streaming and block floating point streaming configurations of the FFT IP. the problem is explained in the following thread: https://community.intel.com/t5/FPGA-Intellectual-Property/FFT-Intel-FPGA-IP-altera-fft-ii-unexpected-source-error-missing/m-p/1406713#M26100 Do you have any idea why would block floating point could generate an missing_sop error in such a design where fixed point do not? I would much appreciate if you can help me with this issue. Best RegardsRe: FFT Intel FPGA IP (altera_fft_ii) unexpected source error (missing sop)
@Kshitij_Intel one more update: if I change the FFT parameters to be <fixed_point>, <variable streaming> instead of <block floating point>, <streaming>, it does not generate the error with all the same timing and signals. But my desired implementation is Block floating point still, so this is to find some more hint about what could have gone wrong. I appreciate if you can help with the problem. Best Regards, Ömer.Re: FFT Intel FPGA IP (altera_fft_ii) unexpected source error (missing sop)
Hello, thank you for feedback, Update: I have cleaned the design on qsys and not anymore having the warnings above, I also got a full license in meantime so no more time limited sof. However the problem still exists and I get exactly the same waveform as above attached. What could I do more to narrow down the problem? Best Regards, Ömer.Re: FFT Intel FPGA IP (altera_fft_ii) unexpected source error (missing sop)
Dear @Kshitij_Intel , The sof is generated with the correct device and programmed via programmer and I have restarted the device and I have tried on different HW but Unfortunately no, the issue is not solved. There are the following critical warnings from compilation report: Could those cause such a problem? Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_1n4096sin.hex -- setting all initial values to 0 Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_2n4096sin.hex -- setting all initial values to 0 Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_3n4096sin.hex -- setting all initial values to 0 Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_1n4096cos.hex -- setting all initial values to 0 Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_2n4096cos.hex -- setting all initial values to 0 Critical Warning(127003): Can't find Memory Initialization File or Hexadecimal (Intel-Format) File /fft_demod_altera_fft_ii_191_vqrjwey_3n4096cos.hex -- setting all initial values to 0 Best Regards,FFT Intel FPGA IP (altera_fft_ii) unexpected source error (missing sop)
Dear Intel FPGA community members, I am getting a strange error from the Intel FFT FPGA IP. The waveform from Signal Tap Logic analyzer is below: I am raising the sink_valid and sink_sop at the same cycle and sink_sop take 1 cycle and valid stays high. after 4 cycles I get the source_error=1 and source_eop pulsed and nothing comes out afterwards from the module. I am using a time_limited ip at the moment but this happens just after I download the sof file and run my application. I hope this is not related to ip evaluation mode. design is running at 250 MHz clock and there is a top level constraint for the clock tree. I create the fft module with tcl script below and instantiate it in my hierarchy. What could be possible reason for such a behavior? I would appreciate if you can help me solving this issue. package require qsys # create the system "fft_ip" proc do_create_fft_ip {} { # create the system create_system fft_ip set_project_property DEVICE {10AX016E3F27I2SG} set_project_property DEVICE_FAMILY {Arria 10} set_project_property HIDE_FROM_IP_CATALOG {true} set_use_testbench_naming_pattern 0 {} # add the components add_instance fft_ii_0 altera_fft_ii 19.1 set_instance_parameter_value fft_ii_0 {data_flow} {Streaming} set_instance_parameter_value fft_ii_0 {data_rep} {Block Floating Point} set_instance_parameter_value fft_ii_0 {design_env} {NATIVE} set_instance_parameter_value fft_ii_0 {direction} {Bi-directional} set_instance_parameter_value fft_ii_0 {dsp_resource_opt} {0} set_instance_parameter_value fft_ii_0 {engine_arch} {Quad Output} set_instance_parameter_value fft_ii_0 {hard_fp} {0} set_instance_parameter_value fft_ii_0 {hyper_opt} {0} set_instance_parameter_value fft_ii_0 {in_order} {Natural} set_instance_parameter_value fft_ii_0 {in_width} {16} set_instance_parameter_value fft_ii_0 {length} {8192} set_instance_parameter_value fft_ii_0 {num_engines} {4} set_instance_parameter_value fft_ii_0 {out_order} {Natural} set_instance_parameter_value fft_ii_0 {out_width} {29} set_instance_parameter_value fft_ii_0 {twid_width} {16} set_instance_property fft_ii_0 AUTO_EXPORT true # add wirelevel expressions # add the exports set_interface_property clk EXPORT_OF fft_ii_0.clk set_interface_property rst EXPORT_OF fft_ii_0.rst set_interface_property sink EXPORT_OF fft_ii_0.sink set_interface_property source EXPORT_OF fft_ii_0.source # set the the module properties set_module_property BONUS_DATA {<?xml version="1.0" encoding="UTF-8"?> <bonusData> <element __value="fft_ii_0"> <datum __value="_sortIndex" value="0" type="int" /> </element> </bonusData> } set_module_property FILE {fft_ip.ip} set_module_property GENERATION_ID {0x00000000} set_module_property NAME {fft_ip} # save the system sync_sysinfo_parameters save_system fft_ip } # create all the systems, from bottom up do_create_fft_ipConduit roles
Hello Everyone, I hope all you are doing great! My question is: I have one component with a conduit which has 3 signals with 3 distinct roles: component1: conduit1 - Conduit Name Role Width Direction Description c1_s1 enable 1 Output no description c1_s2 valid 1 Output no description c1_s3 data 32 Output no description And I have another component with 2 conduits but matching roles to the other component's conduit roles' : component2: conduit1 - Conduit Name Role Width Direction Description c2_s1 valid 1 Input no description conduit2 - Conduit Name Role Width Direction Description c2_s2 data 32 Input no description Now can I connect those two latter conduits to the first conduit and hope Qsys will automatically recognize and connect the lines based on roles? sthg like this: add_connection compnent1.conduit1 component2.conduit1 add_connection component1.conduit1 component2.conduit2 what I would like to have in the end is have the signals connected: c1_s2 connected to c2_s1 c1_s3 connected to c2_s2 (c1_s1 no connection.) Can I do it in this way? If not, what would be the way to achieve this connectivity in the end given such conduit and signal arrangement? Best Regards, Ömer.
