AKhed
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Re: EN2342QI frequency
Hi Mostafa_Intel_AE, Yes i am using that in my design for completing but in this case i am not sure about working frequency regulator and and OCP trip point in this case as these all are interdependent with each other on PVIN,VOUT,RCLX and RFS. it will great if i got some related calculation of those resistor. AjayEN2342QI frequency
I am using EN2342QI 4A PowerSoC Step-Down DC-DC Switching Converter with Integrated Inductor for one of our FPGA base application. I have gone through datasheet and i have understand the most of design process as well as maximum limits. Also i have gone through Table 6. RA, CA, and RCA Values for Various PVIN/VOUT Combinations: Low VOUT Ripple vs. Smallest Solution Size. As this table is for predefine values <1.,1.2,1.5,1.8,2.5,3.3 and 5V and provide related application component. As this chip has variable output range between 0.75 to 5v and depends on voltage divider network. i would like use the this chip for use of 1.35V application and i can calculate the feedback network but i was not able find out the calculation for RFS and RCLX which is external frequency setting resistor and a resistor for adjustment of the over-current protection threshold. i have gone through the some reference schematic of development board which uses the same chip for power generation. it will be helpful if you provide the calculation for these external resistors or any design documents for the same?Re: Clock signal jumper connection
Hello Anand, As I need to interface two source on same differential clocks pin for every clock in available on FPGA and at a time one is present. In my application is clock in either from on board clock generator or from external board and choice is for user who interfacing external board. So, I can't connect both clock source to FPGA. I will check with clock multiplexing IC, still it will increase lot of hardware as I have 4 clock input signals. Does berg pin harm in this condition? if yes what are the different effect on signal can you explain. if I directly merge the signals what are the different effect of same. As I have seen lot of board on which berg pin jumper is used for selection clock source but it have smaller frequency range like 5Mhz. one of the reference from microchip is here. https://www.microchip.com/webdoc/stk500/stk500.clock.settings.htmlClock signal jumper connection
Hello, I am designing Main board using Altera FPGA. In circuit I need external differential clock. On main board I have introduce one clock generator circuit also have provision to take clock from external daughter board. Clock frequency range is 10-200MHz. There are two possibilities but at time one source is selected 1)On board clock generation to FPGA 2)From external board to FPGA In this can I use male berg pin for clock source selection between on board circuit or external board? If I use Berg pin does it affect on clock Signal n any way? one more option to place clock generation circuit near possible to header and directly shorting trace without any jumper? Please suggest any other options
