alexforencich
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Re: 100G E-tile error on Stratix 10 DX
So I did some digging around, and the problem seems to be with how i_ptp_fp was being driven. Apparently something about the soft logic wrapper around the E-Tile ends up requiring that all of the PTP-related input signals are driven by a "hyperflex-friendly register". For reference, the error is associated with the wdata_reg input of alt_ehipc3_mlab #( .WIDTH (TX_PTP_WIDTH), .ADDR_WIDTH (4), .SIM_EMULATE(0) ) ptp_tx_ff ( .wclk (int_tx_clk), .wdata_reg (usr_tx_ptp_ff_in), .wena (tx_ts_ff_write), .waddr_reg (ptp_tx_ff_waddr), .raddr (ptp_tx_ff_raddr), .rdata (usr_tx_ptp_ff_out_wire) ); This is driven by assign usr_tx_ptp_ff_in = {i_ptp_ins_ets, // 1-bit i_ptp_ins_cf, // 1-bit i_ptp_zero_csum, // 1-bit i_ptp_update_eb, // 1-bit i_ptp_ts_format, // 1-bit i_ptp_ts_offset, // 16-bit i_ptp_cf_offset, // 16-bit i_ptp_csum_offset, // 16-bit i_ptp_eb_offset, // 16-bit i_ptp_tx_its, // 96-bit i_ptp_ts_req, // 1-bit i_ptp_fp // 8-bit }; Apparently whatever directly drives these signals must be a simple flip flop with no reset input. Not an MLAB, not an M20K, not even a flip flop with a reset, preset, etc. input. Personally, I consider this to be a bug in the soft logic wrapper. If this MLAB instance needs to be driven by "hyperflex-friendly registers", then such registers should exist in the soft logic wrapper to isolate the upstream logic from the MLAB instances to avoid this kind of difficult-to-debug DRC error. It's unclear why this only seems to be a problem on Stratix 10 devices, but not on Agilex. Anyway, what I ended up doing was adding a register slice across all of the input signals on the transmit side, both the AVST interface and i_ptp_fp. Presumably this will end up being a permanent workaround for this issue.2KViews0likes0CommentsRe: 100G E-tile error on Stratix 10 DX
I'm using 22.1. I have not been using 22.2 due to this issue: https://community.intel.com/t5/Intel-Quartus-Prime-Software/PCIe-HIP-clocking-regression-on-Stratix-10-MX-in-Quartus-Prime/m-p/1394323#M74234 The code that interfaces with the E-tile was developed from scratch based on the documentation for the Agilex F series part, and is used with minimal modification on the Stratix 10 DX. The core logic that does not interface with the E-tile was also written from scratch, but runs and builds correctly on many different FPGAs, including the Stratix 10 DX. The problem is from the E-tile 100G Ethernet IP core. I have not tried to build the example design, but I will give it a shot and see if I can replicate the issue. I suspect that maybe it has to do with some of the unused PTP signals being tied off, instead of being driven by registers. Sure, the Stratix 10 DX and Agilex F are somewhat different, but the E-tile is ostensibly exactly the same on both. And the core logic already works fine on the Stratix 10 DX and 10G and 25G, only difference between 10G/25G/100G in terms of the core logic is clock frequency and datapath width. And the core logic runs correctly on many other FPGAs without any device-specific modifications (Xilinx Virtex 7, Xilinx UltraScale, Xilinx UltraScale+, Intel Stratix 10 MX, Intel Stratix 10 DX, Intel Agilex F).2.1KViews0likes2CommentsRe: Possible Compatibility Issue Between Intel Cyclone 10 GX Dev Kit and Xilinx FMC-105-Debug
From looking at the schematic, it looks like you could probably also put a jumper on J5 between pins 6 and 7 to close the JTAG chain. Schematic: https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/xtp078.pdf1.3KViews0likes0CommentsRe: 100G E-Tile system console connection problem
I'm not sure what the relevance is of AN647, that's for a gigabit interface presumably using a soft MAC, and I'm trying to bring up a 100G interface with the E-tile hard MAC. Anyway, checking with the E-tile example design is a good idea, I'll try that next week and report back if I'm seeing the same issue.773Views0likes0Comments- 2.1KViews0likes0Comments
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Re: 100G E-Tile transceiver adaptation
OS is Linux. I am currently using Quartus Prime Pro 22.1, as 22.2 is broken (see https://community.intel.com/t5/Intel-Quartus-Prime-Software/PCIe-HIP-clocking-regression-on-Stratix-10-MX-in-Quartus-Prime/m-p/1394323#M74234). You guys sent me a DE10-Agilex rev B instead of a rev C, so I have an ES part (AGFB014R24A2E2VR0) instead of a production part (AGFB014R24B2E2V). The code is here: https://github.com/alexforencich/corundum/tree/master/fpga/mqnic/DE10_Agilex/fpga_100g I'll generate a QAR soon.1.1KViews0likes0CommentsRe: 100G E-Tile transceiver adaptation
Minor update to this, just to rule out some possible settings combinations: "Adaptation load soft IP" off, xcvr_reconfig tied off (no reconfig logic): no link, need to adjust adaptation settings in system console to get an RX link "Adaptation load soft IP" on and NRZ_28Gbps_LR selected and settings saved in config 0, xcvr_reconfig tied off (no reconfig logic): no link, need to adjust adaptation settings in system console to get an RX link "Adaptation load soft IP" on and NRZ_28Gbps_LR selected and settings saved in config 0, xcvr_reconfig connected to state machine: no link, need to adjust adaptation settings in system console to get an RX link (and state machine is stuck trying to trigger the PMA configuration streamer, which never appears to start) Hardware config: FPGA (DE10-Agilex rev B with AGFB014R24A2E2VR0) E-Tile -> QSFP-DD cage -> QSFP28 DAC -> Mellanox ConnectX-5 NIC In this case, the ConnectX-5 reports that the link is up at 100 Gbps, but rx_pma_ready on the E-Tile is low. If take the settings that the transceivers get when in 25G mode and apply them via the system console, then the link does come up. Question is how to do that without involving the system console. Edit: and I just tested with a 30M AOC, and I was able to get a link. So, apparently the default parameters on the E-Tile transceivers will work with AOCs with integrated CDRs, but not DACs. However, the same exact DAC works perfectly with Xilinx UltraScale+ devices at 100G, and with the E-Tile at 25G (with the adaptation load soft IP working to configure the transceivers), so it seems like the E-Tile should be able to work in this situation.1.1KViews0likes0Comments