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Mahdi

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Re: Initialize EMIF example memory model
Hi Adzim, I guess this will work as well. Thanks for sharing the link. - Mahdi
3 years ago Place IP & Transceiver
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Re: Initialize EMIF example memory model
Hi Adzim, Thanks for your reply. When you generate an EMIF example for the purpose of simulation, it will generate a memory model to work with. I am referring to this memory model, and I want to know if there is any way to initialize this memory. Please take a look at this: https://www.intel.com/content/www/us/en/docs/programmable/683842/21-1-19-2-0/simulation-example-design.html Thanks, Mahdi
3 years ago Place IP & Transceiver
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Initialize EMIF example memory model
Hi, Is there any way to initialize the EMIF example memory model for simulation in Modelsim? I want to read specific data from memory. Thanks, Mahdi
Solved
3 years ago Place IP & Transceiver
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Re: Understanding address map in EMIF
Oh, I see. I did not know this fact. Thank you so much for your explanation. - Mahdi
3 years ago Place Boards & Dev Kits
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Re: Understanding address map in EMIF
Hi Adzim, Thanks for your reply. I am not using the actual memory system. I am using the memory IP core that is generated in EMIF design example, and I do not know its specifications. - Mahdi
3 years ago Place Boards & Dev Kits
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Understanding address map in EMIF
Hi, I am trying to read/write from/to an external memory model during the simulation using EMIF. I have some questions regarding the address map in EMIF. Based on this configuration, what should be the address width? I guess it should be 29 bits, right? But, why the amm_address is 26 bits here? Also, I can't understand why mem_a is 17 bits. The other problem is that I don't know how to generate certain addresses if I want to read or write from/to memory. What is the meaning of each bit of this 26-bit amm_address? Here is the Controller configuration: Thank, -- Mahdi
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3 years ago Place Boards & Dev Kits
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Simulating the behavior of external memory
Hi, I am wondering if there are any ways to simulate the behavior of external memory (DRAM with DDR4 protocol) on Intel Stratix 10 FPGA. I know that I can simulate the EMIF itself, and I have already connected the EMIF to my design. But I do not know how to simulate the DRAM as well without connecting the design to the actual FPGA board. Thanks, - Mahdi
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3 years ago Place Boards & Dev Kits
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Re: connecting Stratix 10 External Memory Interface (EMIF) to multiple AV-MM
Thank you so much for your help!
3 years ago Place IP & Transceiver
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Re: connecting Stratix 10 External Memory Interface (EMIF) to multiple AV-MM
Thanks for your reply, but my question is whether I can connect three AV-MM Master ports to this AV-MM slave. If not, how can I do this?
3 years ago Place IP & Transceiver
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connecting Stratix 10 External Memory Interface (EMIF) to multiple AV-MM
Hello, I have a design with two AV-MM read ports and one write port, including read_data_valid and write_data_valid, and separate watirequest for each port. All these three ports are master ports, which should be connected to slave ports. I am wondering how I can instantiate an EMIF that can support this kind of design and have an arbiter to which I can connect all these three ports to it. I want to use the DDR4 protocol for my design. I could not find anything useful in the UG of EMIF, and it is not clear in Platform Designer whether I can have this kind of interface or not. I will be glad if somebody can help me with this issue. Thanks, -- Mahdi
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3 years ago Place IP & Transceiver
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