ContributionsMost RecentMost LikesSolutionsRe: Modelsim Simulation error Hi @sstrell , Thank you so much for your reply! I tried to toggle the switch, with the following modified code, but still I have the same issue. Is there anything else that I've done wrong or maybe there's anything more I should add? `timescale 1 ps / 1 ps module fpmulttrial_tb(); reg [63:0] dataa, datab; reg clk; wire [63:0] result; fpmult1try UUT( .dataa(dataa), .datab(datab), .clock(clk), .result(result)); always #100 clk= ~clk; initial begin clk=1; dataa= 000; datab= 10.97; #100 dataa= 7; datab= 19.97; #100 dataa= 9; datab= 109.7; #100 dataa= 10; datab= 1.97; #100 dataa= 4; datab= 1.7; #100 dataa= 9; datab= 19.9797; #100 dataa= 3; datab= 9.7; #100 $finish; end endmodule Thanks a bunch! Best Regards, Shainy Modelsim Simulation error Hi, I've been trying to simulate an IP core on Modelsim. The IP core I'm using is ALTFP_MULT IP core (floating-point multiplier), with double precision and an output latency of 5(the lowest latency possible). And below is the testbench I created for simulation purposes on Modelsim. The issue is that, as shown in the image, when I try to run this, only a blue line is visible as the output. Really appreciate if someone could kindly help me figure out what's wrong with my testbench/modelsim simulation. Thanks in advance! [dataa/datab= input data || result= output of the multiplier] `timescale 1 ps / 1 ps module fpmulttrial_tb(); reg [63:0] dataa, datab; reg clk; wire [63:0] result; fpmult1try UUT( .dataa(dataa), .datab(datab), .clock(clk), .result(result)); initial begin clk=1; dataa= 000; datab= 10.97; #100 dataa= 7; datab= 19.97; #100 dataa= 9; datab= 109.7; #100 dataa= 10; datab= 1.97; #100 dataa= 4; datab= 1.7; #100 dataa= 9; datab= 19.9797; #100 dataa= 3; datab= 9.7; end endmodule Re: Floating-Point IP for FIFO Buffer Hi Chee Pin, Thank you so much for your reply. Yes, as you've mentioned there wasn't any ip mentioned on the user guide, so I guess there is no ip for it. But I tried running the the following code to build a buffer, and there were no errors that came up. But, when I give in values on the test bench and simulate through Modelsim, it gets rounded to the closest integer. Is there anything wrong with my code or is there any advice that I could use, to display a floating-point number instead of the closest integer value? `define BUF_WIDTH 3 `define BUF_SIZE ( 1<<`BUF_WIDTH ) module FifoBuffer2( clk, reset, in_x, out_x, write, read, emp, full); input reset, clk, write, read; input [8:0] in_x; output [8:0] out_x; output emp, full; reg[8:0] out_x; reg emp, full; reg[`BUF_WIDTH -1:0] rd_ptr, wr_ptr; reg[8:0] buf_mem[`BUF_SIZE -1 : 0]; always @(posedge clk) begin if( write && !full ) buf_mem[ wr_ptr ] <= in_x; else buf_mem[ wr_ptr ] <= buf_mem[ wr_ptr ]; end always @(posedge clk) begin if( reset ) begin wr_ptr <= 0; rd_ptr <= 0; end else begin if( !full && write )wr_ptr <= wr_ptr + 1; else wr_ptr <= wr_ptr; if( !emp && read ) rd_ptr <= rd_ptr + 1; else rd_ptr <= rd_ptr; end end endmodule Re: Using IPs on a Verilog code Will try this. Thank you so much! Re: Using IPs on a Verilog code Hi Sstrell, Thank you for your reply! I'm actually a bit lost on how to use the ip I've created on my verilog code. I tried looking for ways and examples on the internet, but I was not able to. Am I to use it as a library, or a module, or a function, or am I supposed to instantiate it in a module? Thanks, Shainy Using IPs on a Verilog code Hi, I'm using an IP for a multiplier and an accumulator, and I'm quite unsure of how to use it in my Verilog code. I built a block diagram for it, but I need to control the number of times these 2 ips function, before they're reset. To give a little background, I want the multiplier to multiply n number of values sets, and send them to the accumulator, which will accumulate the the n number of values sent, and send the final value to the output buffer. Could someone kindly guide me on the steps to be taken? Thanks a bunch! Best Regards, Shainy Floating-Point IP for FIFO Buffer Hi, I'm suing Quartus Prime Lite 18.1 and using a Cyclone V device. I was searching for a floating-point ip for a fifo buffer, but was unable to find one. But I did see a fifo buffer ip 'FIFO' under on chip memory. Could someone confirm if this could be used for floating point values as well, or if there is a different ip that I could use? Thanks in advance! Best Regards, Shainy Re: ALTMULT-ACCUM (Multiplier-accumulate) Alternative Hi Nurina, Thank you so much for the guidance! I'll refer to the document given above. Thanks again! Best Regards, Shainy ALTMULT-ACCUM (Multiplier-accumulate) Alternative Hi all, I'm a newbie, using Quartus Prime Lite 18.1, and my device is of Cyclone V family. I need to build a multiplier-accumulator, and learnt that the IP catalog consists of an arithmetic megafunction; ALTMULT-ACCUM. But when referring to the 'Integer Arithmetic Megafunctions User Guide' it mentions that Quartus Prime 13.1 upwards do not support this megafunction for cyclone V, instead use ALTMULT_ADD (Mulitply- Adder). But, when I try to use this function on Quartus, it says that this is not supported for cyclone V anymore. I'd like to know if there is any alternative that I could use or if there is a way to create a megafunction or a way to get around this issue. Hoping someone could help me in figuring this out. Thanks in advance!! Best Regards, Shainy SolvedRe: Having a problem when creating a new Nios ii Application and BSP from template Hi, I face the same issue with Eclipse, and really appreciate if someone could let me know a fix to this. Thanks in advance! Regards, Shainy