Parisa
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Index out of range in for loop
Hi everyone, I have a code that has a for loop within an if condition. the for loop starts at 0 and is suppose to go up to less than (length_in - 1). length_in is an input and can have max value of 20. so the loop is suppose to start at 0 and in worst case scenario go up to less than 19 which means 0 to 18. but I get an error that index [19] is out of range [18:0] when I try to synthesize the code on quartus pro 20.1. even when I make it length_in - 10, I still get this error. Can someone help me please? the code is: if(pure ==0) begin for(i-0; i<length_in-1; i=i+1)begin gini_impurity = (count_one[i]*count_zero[i])\(count_one[i]+count_zero[i]); end end the error is index [19] is out of range [18:0] for count_one1.6KViews0likes3CommentsModelsim Input Matrix
I do have a matrix input in my code in system verilog and modelsim does not show the matrix input in simulations. when I cahnge the matrix form to an array, then it is shown in the input in simulation Can someone tell me why is that and help me to fix it? Thank you The input not shown in simulation because it is a matrix: input wire [DATA_WIDTH-1:0] instances [CHAN_NUM-1:0], The input shown when it is an array: input wire [DATA_WIDTH*CHAN_NUM-1:0]instances,3.4KViews0likes2Commentsunable to create symbol file for current file (Verilog HDL file) in Quartus prime pro 20.3
Hi everyone, I am working on Quartus prime pro 20.3 and I was going through "my first fpga tutorial". Here it says after creating simple_counter.v verilog code, we need to go to create/update and create block diagram for current file. My whole create/update file is disabled and I even in disable mode, I dont even have the option to create block diagram for current verilog file can anyone help me? Thank you1.5KViews0likes2Comments