sa_lahrich
New ContributorJoined 5 years ago
User Profile
New Contributor
User Widgets
Contributions
Nios II Debug : No source available for ""
Hi, I am facing an issue with Nios II Debugger. Actually, I am using Cyclone V SoC Development Kit. I dowloaded the .sof of quartus project and I would like to debug the C code. Unfortunately, when I launch the Debugger, I have an error message without any explanation No source available for "" When I click on View disassembly, nothing happens. I treid to clean and refresh the project, the error is always here. I even tried to rebuild new quartus and Nios II project in a new workspace, it did not change anything. I do not know if I am missing something, does someone have any idea to fix the issue ? Thanks in advance, Regards,1.8KViews0likes3CommentsSingle Ended Clk to Differential clock
Hi, I am working on Cyclone V SoC Development Kit, using the High Speed Mezanning Card (HSMC Board). I have to respect the order of LVDS inputs, the LVDS input clock must be in the middle of incoming signals. I thought of using HSMA_CLK_IN_P1 and HSMA_CLK_IN_N1 of the HSMC Board but this pair cannot be connected get a LVDS value on the FPGA. I was wondering if I can use 9 signals of Bank 3 of the HSMC port with the clock in the middle... In other words, use any pair (HSMA_RX_D_PX,HSMA_RX_D_NX) and assign it to this differential clock. Thanks in advance,Solved1.3KViews0likes2Comments