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syam
Occasional ContributorJoined 5 years ago
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CYCLONE V HPS Boot - SDRAM Size Check Failed
Hi I have an CYCLONE V FPGA design that was compiled using Quartus 20.1.1. The RBF is working since we had tested this independently using old Quartus 18.1 boot flow. Now we are trying to boot with new boot flow mentioned here. But after we generate the files, create the SD card image and power up the boot is failing with the following error. A similar error is documented by Intel for Arria 10 FPGA here. When we tired to apply the patch here to the uboot code it failed. This could be because ours is a Cyclone V design for which this patch doesn't apply. Please show a way forward. Best Regards SyamRe: Quartus 18.1 - CYCLONE V Preloader issue
Migrated my FPGA design to Quartus 20.1.1, compiled and generated the RBF and tested with old 18.1 boot flow. The RBF is working. Then I followed the latest boot flow you suggested. Generated the files required. Now right at power up and boot up I am seeing this error. I found this article - https://www.intel.ca/content/www/ca/en/support/programmable/articles/000073948.html which points to a similar error. There it is suggested that a bug exist with uboot source code. Also a patch is given. But it seems it is related to Arria10 and not Cyclone V which am working with. But I tried applying it but it didn't get applied. May be because it is intended for Arria10 only. Any help would be much appreciated. Best Regards SyamQuartus 20.1.1 - Error in HDL generation from Platform Designer
Hello I am compiling my project using Quartus 20.1.1. My Windows build info is given below. Following the thread here where a similar error is described I have also done the following. I also tried the hacks mentioned in there. But the error persists. Please help. I have attached the full error log from platform designer for reference. Best Regards Syam
