Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!
Data Parallel C++ (DPC++) is an open-source compiler project based on the Khronos SYCL compiler with a few extensions. It is also the foundation compiler technology for oneAPI, a cross-industry, open, standards-based unified programming model that delivers a common developer experience across accelerator architectures. SYCL is an industry-driven Khronos programming language standard that adds data parallelism to the C++ language with support for heterogeneous computing architectures. The DPC++ language also offers broad, heterogeneous support for CPUs, GPUs, and FPGAs – which is why it’s the compiler at the core of the oneAPI specification. Springer has just published new book titled “Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL” under its Apress open-access imprint. The book’s authors include James Reinders, a consultant with more than three decades of parallel computing experience, and five additional authors from Intel. A printed version of the book is now on sale online and a free PDF version is available on the SpringerLink Web site under the Creative Commons Attribution 4.0 International License. This new 548-page book covers programming for data parallelism using C++ in depth. All examples in the book starting with the “Hello Data-Parallel Programming World” example in Chapter 1 compile and work with DPC++ compilers and are available from a GitHub repository. The book is for all software developers, whether they’re new to parallel programming or old hands at it. As the authors write in the book’s preface: “If you are new to parallel programming, that is okay. If you have never heard of SYCL or the DPC++ compiler, that is also okay.” For readers of this Programmable Logic blog, Chapter 17 titled “Programming for FPGAs” will be especially interesting. As the authors explain in Chapter 17’s second paragraph: “Field Programmable Gate Arrays (FPGAs) are unfamiliar to the majority of software developers, in part because most desktop computers don’t include an FPGA alongside the typical CPU and GPU. But FPGAs are worth knowing about because they offer advantages in many applications. The same questions need to be asked as we would of other accelerators, such as “When should I use an FPGA?”, “What parts of my applications should be offloaded to FPGA?”, and “How do I write code that performs well on an FPGA? “This chapter gives us the knowledge to start answering those questions…” For more information about “Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL,” and to download a free PDF copy of the book, click here. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
oneAPI and SIMD Instructions are a natural fit for database acceleration on Intel FPGAs
Single Instruction Multiple Data (SIMD) is a cutting-edge technique for enhancing the computational performance of single-threaded tasks on modern CPUs. FPGAs are renowned for delivering high-performance computing by tailoring circuits to specific algorithms. They provide a customized and optimized hardware solution, which can significantly accelerate complex computations.IEEE FPGA Workshops and Tutorials featuring Intel speakers, May 9-13
The virtual 29th IEEE International Symposium On Field-Programmable Custom Computing Machines (FCCM) takes place online from May 9-12. Intel speakers will be presenting several workshops and tutorials at this conference including: Intel FPGA Cloud Services and Remote Learning – Workshop – May 9 AI Optimized Intel® Stratix® 10 NX FPGA – Tutorial – May 12 Using Intel® oneAPI Toolkits with FPGAs – Workshop – May 12 For more information about these IEEE FCCM workshops and tutorials including registration details, click here. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.The Three Levels of Heterogeneity: Devices, Systems, and Software
By Jose Alvarez, Senior Director, Intel CTO Office, PSG The following blog is adapted from a keynote speech that Jose Alvarez presented as the recent The Next FPGA Platform event, held in San Jose, California. There are three levels of heterogeneous integration. It’s a simple taxonomy. First, there’s heterogeneous integration at the chip level – the device level. Second, there’s heterogeneous integration at the system level. And third, there’s heterogeneity at the software level. Heterogeneity at all three levels lead to system reconfigurability. The First Level: Chip Heterogeneity Chip-level heterogeneity is heterogeneous integration inside of the device package and is closely tied to the concept of chiplets. We're building much more complex systems, much larger systems, and building larger systems with big, monolithic semiconductors is difficult. The yields for large die are not as good as for smaller die, or for chiplets. It's far more practical, more economical, to build these systems with smaller components. From a system perspective, we can make better semiconductor design decisions using chiplets because we don't have to redesign every chiplet from one semiconductor process node to the next. Some functions work perfectly well in their existing form. There’s no reason to redesign these functions when a newer technology node comes on line. Heterogeneous integration is already in production. It’s a very important technology and Intel is committed to a chiplet-based design strategy. For example, Intel® Stratix® 10 FPGAs and Intel® Agilex™ FPGAs are based on heterogeneous integration and these devices are in production now. In fact, the Intel Stratix 10 FPGAs have been in volume production for years. Chiplet-based IC design and manufacturing permit Intel to build systems with silicon-proven functions including high-speed serial transceivers, memory interfaces, Ethernet and PCIe ports, et cetera. Chiplet-based designs also permit Intel to develop targeted architectures for different workloads and bring them to market more quickly. For these reasons, Intel is actively encouraging the development of an industry ecosystem based on chiplets. We do that in in several ways. For example: Intel developed Embedded Multi-die Interconnect Bridge (EMIB) technology, an embedded multi-chip interconnect bridge used to interconnect chiplets with a standardized interconnect. Intel developed the Advanced Interface Bus (AIB), which is a PHY that Intel released as an open-source, royalty-free, high-performance chiplet interconnect. Intel recently joined the CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance, which is a collaborative industry organization dedicated to encouraging chiplet-based development. Coincidentally, Gordon Moore, one of our founders, published a paper in 1965 titled “Cramming more components onto integrated circuits.” It was a very short paper; only four pages, including pictures, and it became very famous. The second page of this famous paper contains a statement that became known as Moore’s Law: “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.” Moore’s statement predicts the exponential increase in semiconductor technology that’s now lasted, not for 10 years, but for more than 50 years! The third page of Moore’s paper goes on to mention that, just possibly, it might be better to build larger systems using smaller components integrated into a single package: “It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected. The availability of large functions, combined with functional design and construction, should allow the manufacturer of large systems to design and construct a considerable variety of equipment both rapidly and economically.” Even back in 1965, Gordon Moore knew that chip-level, heterogeneous integration would be a way to move forward. This is what Intel is doing today: using advanced packaging to bring all of the company’s technologies to bear in one IC package. The Second Level: System Heterogeneity The second heterogeneous integration level is at the system level. We live in a data-centric world today. There's data everywhere. Intel is driving a lot of innovation at the system level to handle this deluge of data. A lot that needs to be done with this data: move it, store it, process it. Workloads associated with these tasks require many solutions and Intel develops and makes a wealth of devices to perform these tasks – CPUs, GPUs, ASICs, FPGAs – that we use to build heterogeneous systems. These varied workloads require different processing architectures. Scalar workloads run well on CPUs. Vector workloads run well on GPUs. Matrix workloads including AI and machine learning often run best on workload-specific ASICs. Finally, spatial workloads are best run on an FPGA. So it is important to have all of these heterogeneous architectures available to provide the right architecture for specific workloads in the data center. Bringing CPUs, GPUs, FPGAs, and specialized accelerators together allows Intel and its customers to solve problems intelligently and efficiently. The Third Level: Software Homogeneity The third type of heterogeneous integration is at the software level. This one’s hard. Intel’s approach is called the oneAPI initiative, a cross-industry, open, standards-based unified programming model that addresses the fundamental way that we build software today, which is akin to cooking. In the kitchen, you don’t ask chefs whether they have a specific way of “building” food. They have many, many ways of using tools, selecting ingredients, and preparing food to create an infinite variety of meals. Similarly, I think that we'll continue to use a multitude of programming and description languages in the future. What developers hold dear is having a single, unified development environment. That’s what Intel is striving for with the oneAPI initiative. That’s the vision. And this vision addresses the four workload types mentioned earlier: scalar, vector, matrix, and spatial. The oneAPI initiative provides a level of abstraction so that, in principle, a software developer can develop code in one layer and then deploy that code to the many processing architectures mentioned above. Today, it's just a start. Intel just announced the open-source oneAPI initiative a few weeks ago along with a beta-level product called the Intel® oneAPI Toolkits. We expect that developing Intel oneAPI Toolkits will be a long road and we definitely understand the journey we’re making. Today, we have Data Parallel C++ and libraries for the Intel oneAPI Toolkits. Data Parallel C++ incorporates SYCL from the Khronos Group and supports data parallelism and heterogeneous programming. Data Parallel C++ allows developers to write code for heterogeneous processors using a “single-source” style based on familiar C++ constructs. The Three Heterogeneous Levels Together At Intel, we know that these three levels of heterogeneity are very important for the industry. That’s why we focus at the chip level on advanced packaging technologies, at the system level on multiple processing architectures, and at the software level with the oneAPI initiative and the Intel oneAPI unified programming environment and Data Parallel C++ programming language. Intel sees a semiconductor continuum where nascent markets – for example machine learning, AI, and 5g – require flexibility in terms of rapidly changing interfaces and workloads. FPGAs play a role in the early stages of these markets because of their extreme flexibility. As these markets grow, companies developing systems for these markets often develop custom ASICs. Intel serves these markets with Intel® eASIC® structured ASICs and full custom ASICs that deliver reduced power and better performance. The Intel development flow permits a smooth progression from FPGAs into pin-compatible Intel eASIC devices and ultimately into ASICs as markets mature and production volumes grow. Intel eASIC devices work well in the data center as well, where multiple applications with specific workloads require acceleration. An accelerator design implemented with an FPGA can become a chiplet based on Intel eASIC technology. That chiplet can be faster and use less power than the FPGA, and it can be integrated into a package with other devices using AIB or some other interconnect method. For more information on Intel oneAPI Toolkits and Data Parallel C++, see “Intel announces open oneAPI initiative and development beta release with Data Parallel C++ language for programming CPUs, GPUs, FPGAs, and other accelerators” and “Want a longer, more detailed explanation of the oneAPI unified programming model? Here’s a 30-minute video.” Legal Notices and Disclaimers: Intel technologies’ features and benefits depend on system configuration and may require enabled hardware, software or service activation. Performance varies depending on system configuration. No product or component can be absolutely secure. Check with your system manufacturer or retailer or learn more at intel.com. Results have been estimated or simulated using internal Intel analysis, architecture simulation and modeling, and provided to you for informational purposes. Any differences in your system hardware, software or configuration may affect your actual performance. Intel does not control or audit third-party data. You should review this content, consult other sources, and confirm whether referenced data are accurate. Cost reduction scenarios described are intended as examples of how a given Intel- based product, in the specified circumstances and configurations, may affect future costs and provide cost savings. Circumstances will vary. Intel does not guarantee any costs or cost reduction. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Altera is a trademark of Intel Corporation or its subsidiaries. Cyclone is a trademark of Intel Corporation or its subsidiaries. Intel and Enpirion are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Parallel computing expert James Reinders says that XPUs are the Future of Compute
James Reinders, a 27-year Intel alum who recently rejoined Intel after a four-year stint as a parallel computing consultant and expert, recently wrote and published a comprehensive book about Data Parallel C++ (DPC++) titled “Data Parallel C++: Mastering DPC++ for Programming of Heterogeneous Systems using C++ and SYCL” (see “Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!”). DPC++ allows software developers to create code using a “single-source” writing style that can then generate parallel run-time code for heterogeneous processors including CPUs, GP-GPUS, FPGAs, and other hardware accelerators. As a class, Intel calls these processors “XPUs.” Now, Reinders has published an article titled “Heterogeneous Processing Requires Data Parallelization: SYCL and DPC++ are a Good Start” that provides a quick introduction to the XPU concept and looks at the future of heterogeneous parallel programming. In this article, Reinders writes: “SYCL and DPC++ will help us make effective use of XPUs. They are part of a broader push for support of XPUs that extends into libraries and all software development tools, building on the ambitions of SYCL and its compilers.” He continues: “That is the origin of the oneAPI industry initiative, which I’m really passionate about and was excited to be a part of as I rejoined Intel.” Later, in the article’s conclusion, Reinders writes: “I hope you’ll take the opportunity to get educated about SYCL, DPC++ and oneAPI because XPUs are the future of compute.” If you want to understand what has gotten Reinders so excited about XPUs, DPC++, and the oneAPI initiative, then give his article a read. Notices and Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.NextPlatform.com article describes Intel® oneAPI use at CERN for Large Hadron Collider (LHC) research
Independent consultant James Reinders has just published a comprehensive article on the NextPlatform.com Web site titled “CERN uses [Intel®] DL Boost, oneAPI to juice inference without accuracy loss,” which describes the use of deep learning and Intel® oneAPI by CERN to accelerate Monte Carlo simulations for Large Hadron Collider (LHC) research. Reinders writes that CERN researchers “have demonstrated success in accelerating inferencing nearly two-fold by using reduced precision without compromising accuracy at all.” The work is being carried out as part of Intel’s long-standing collaboration with CERN through CERN openlab. If Reinders’ name looks familiar to you, that’s because he recently published a book about the use of Data Parallel C++ (DPC++), which is the foundation compiler technology at the heart of Intel oneAPI. (See “Springer and Intel publish new book on DPC++ parallel programming, and you can get a free PDF copy!”) CERN researchers found that about half of the computations in a specific neural network (NN) called a Generative Adversarial Network (GAN) could be switched from FP32 to INT8 numerical precision, which is directly supported by Intel® DL Boost, without loss of accuracy. GAN performance doubled as a result while accuracy was not affected. Although this work was done using Intel® Xeon® Scalable Processors with direct INT8 support, Reinders’ article also makes the next logical jump: “INT8 has broad support thanks to Intel Xeon [Scalable Processors], and it is also supported in Intel® Xe GPUs. FPGAs can certainly support INT8 and other reduced precision formats.” Further, writes Reinders: “The secret sauce underlying this work and making it even better: oneAPI makes Intel DL Boost and other acceleration easily available without locking in applications to a single vendor or device” “It is worth mentioning how oneAPI adds value to this type of work. Key parts of the tools used, including the acceleration tucked inside TensorFlow and Python, utilize libraries with oneAPI support. That means they are openly ready for heterogeneous systems instead of being specific to only one vendor or one product (e.g. GPU). “oneAPI is a cross-industry, open, standards-based unified programming model that delivers a common developer experience across accelerator architectures. Intel helped create oneAPI, and supports it with a range of open source compilers, libraries, and other tools. By programming to use INT8 via oneAPI, the kind of work done at CERN described in this article could be carried out using Intel Xe GPUs, FPGAs, or any other device supporting INT8 or other numerical formats for which they may quantize.” For additional information about Intel oneAPI, see “Release beta09 of Intel® oneAPI Products Now Live – with new programming tools for FPGA acceleration including Intel® VTune™ Profiler.” You may also be interested in an instructor-led class titled “Using Intel® oneAPI Toolkits with FPGAs (IONEAPI).” Notices & Disclaimers Performance varies by use, configuration, and other factors. Learn more at www.Intel.com/PerformanceIndex. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. Gold Release of Intel® oneAPI Toolkits arrive in December: One Programming Model for a Heterogeneous World of CPUs, GPUs, and FPGAs
This week at the Supercomputing 2020 (SC20) conference, Intel announced that the gold release of the Intel® oneAPI toolkits will become available next month. The oneAPI industry initiative is creating a unified and simplified cross-architecture programming model that delivers uncompromised performance without proprietary lock-in, while allowing you to integrate legacy code. Intel oneAPI Toolkits allow you to create code for CPUs and XPUs (the term “XPU” means “other processing units”) – such as GPUs based on the Intel® Xe architecture and Intel® FPGAs including Intel® Arria® and Intel® Stratix® FPGAs – within a unified programming environment. With oneAPI, you choose the best processing architecture for the specific problem you’re solving without needing to rewrite software. Intel oneAPI toolkits take full advantage of cutting-edge hardware capabilities and instructions built into Intel® CPUs including Intel® AVX-512 SIMD instruction extensions and Intel® DL Boost, along with features unique to Intel® XPUs. Built on long-standing and proven Intel developer tools, Intel oneAPI toolkits support familiar languages and software standards while providing full continuity with existing code. The gold release of Intel oneAPI toolkits will start shipping in December. They will be available for free, to run locally and in the Intel® DevCloud. Commercial versions that include worldwide support from Intel technical consulting engineers will also be offered. For more information about this and other Intel SC20 announcements, click here. Notices & Disclaimers Performance varies by use, configuration and other factors. Learn more at www.Intel.com/PerformanceIndex. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. See backup for configuration details. No product or component can be absolutely secure. Your costs and results may vary. Intel technologies may require enabled hardware, software or service activation. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others. World-Changing Technology to Enrich People’s Lives: Architecture Day 2020, the Six Key Intel Technology Pillars, and Intel® FPGAs
Earlier this month during Architecture Day 2020, Intel’s Chief Architect Raja Koduri and a dozen Intel fellows and architects discussed numerous advanced technologies that the company has developed and is developing so that it can continue to deliver solutions for our customers’ greatest challenges. These many advanced technologies comprise the six key pillars of innovation that collectively embody the focus of the company’s engineering development work: Process and Packaging XPU Architecture Memory Interconnect Security Software All six of these pillars are essential to creating the solutions that fuel Intel’s purpose: To create world-changing technology that enriches the lives of every person on earth. Perhaps the most broadly discussed of these six pillars is semiconductor process technology; That technology pillar has certainly been an Intel crown jewel for more than half a century. During Architecture Day 2020, Ruth Brain, Intel Fellow and Director of Interconnect Technology and Integration at Intel, discussed the company’s new 10nm SuperFin technology, which represents the largest single intranode process technology enhancement in the company’s history. Intel’s 10nm SuperFin process technology delivers performance improvements comparable to a full-node transition by incorporating several innovations including: An improved finFET gate process that results in higher electron mobility and faster transistors Self-aligned quad patterning, which nearly doubles the scaling density of the critical M0 and M1 layers in the metal stack Cobalt local interconnects, which halve via resistance and reduce electromigration by a factor of 5X to 10X COAG (contact over active gate) design, which further reduces cell size and improves transistor density by relocating the finFET’s gate contact from its previous location next to the transistor to a spot directly over the transistor’s gate, thus reducing the amount of real estate consumed by each transistor These and other innovations in the Intel 10nm SuperFin process technology demonstrate that feature size is not the only significant parameter when it comes to improving performance. In a nearly prescient article titled “No More Nanometers” published only a couple of weeks before Architecture Day 2020, EEJournal’s Kevin Morris describes the essence of the Intel six-pillar strategy when he wrote: “For the previous three decades, there was little reason to optimize … anything, really. After all, why spend a huge amount of energy doing a 15-20% improvement that would simply be obliterated by the 2x bounty of the next Moore’s Law node, and another 2x two years after that? We simply focused on building the functionality we needed and relied on lithography progress to make it faster, cheaper, and more power efficient. Now, however, we engineers couldn’t just ‘phone it in’ anymore. We had to come up with new and novel ways to improve performance and reduce power consumption, rather than relying on the penumbra of Moore’s Law to get us past the finish line in our system designs.” In a follow-on EEJournal article titled “Intel – Flourish or Flounder,” which also appeared before Architecture Day 2020, Morris wrote: “The big gains in process technology have been from innovations such as finFETs and other advances that don’t relate to geometry shrinks.” This sentence succinctly describes the approach taken in the development of Intel’s 10nm SuperFin process technology. (Note: Morris’ opinions as expressed in his second article firmly fall on the “flourish” side of its headline’s implied question.) Press and analyst reaction to the Architecture Day 2020 discussion of the 10nm SuperFin process improvements has been very positive. Here are a few quotes: “Intel's improvements in the 10nm process and architecture are so significant that the company is claiming a nearly 20% performance improvement over 14nm. With 14nm, Intel made small incremental performance improvements of roughly 4-5% per refresh (+++), which amounted to about 20% across four different CPU architectures. Intel is achieving this with a single step rather than four, which is what makes this transition to 10nm much more significant than many realize.” – Patrick Moorhead, Forbes “Pursuing more cost-effective methods of interconnection and aggregation is how we’ll drive down the cost of mounting memory closer to the CPU and improving overall performance characteristics. The work Intel is talking about on the interconnect front is critical to long-term performance improvements and better power efficiency.” - Joel Hruska, ExtremeTech “Intel's advanced packaging technologies will allow it to mix and match IP and process nodes from other vendors into the same heterogeneous packages, yielding time to market advantages.” – Paul Alcorn, Tom’sHardware “In terms of the wrap-around process, with the support of architecture and technology, Intel's 10nm is far more powerful than imagined, and the final judgment standard still needs to be based on the performance of the whole set.” – Fu Bin, 21ic Electronic Network However, semiconductor process technology constitutes only part of the first Intel technology pillar. Packaging technology constitutes the other part – a co-equal part – of the pillar. There are big performance, power, and cost gains to be achieved from packaging improvements. That’s why the next Architecture Day 2020 talk – presented by Ramune Nagisetty, Senior Principal Engineer and Director of Product and Process Integration at Intel – discussed several of the many packaging innovations that Intel has developed, including: EMIB (Embedded Multi-die Interconnect Bridge) and AIB (Intel's Advanced Interface Bus), which are used to combine several semiconductor die in one package using 2.5D packaging technology Foveros technology, which extends chip packaging into the 3 rd dimension Hybrid bonding, which further improves 3D chip packaging Co-EMIB, which blends 2D, 2.5D, and 3D packaging techniques to enable the creation of a larger-than-reticle sized base with high-density connections among companion die and stacked-die complexes Intel has used the EMIB and AIB packaging technologies for heterogeneous integration in FPGA development for several years. The Intel® Stratix® 10 and Intel® Agilex™ FPGA families employ heterogeneous packaging as a foundation technology to combine FPGA base die with a variety of advanced I/O die to add features such as 116 Gbps SerDes transceivers, PCIe Gen5 ports, and UPI and CXL coherent processor attach ports. Heterogeneous integration is also a key technology used in the creation of the Intel Stratix 10 MX FPGA, which adds high-speed HBM2 memory die stacks to the mix. Intel’s advanced packaging technology makes it possible to create broad, diverse product families and bring them to market quickly. For example, heterogeneous integration accelerated the development and recent introduction of the newest member of the Intel Stratix 10 FPGA family – the Intel Stratix 10 NX FPGA – which changes out the existing FPGA die in the Intel Stratix 10 MX FPGA with a newly designed FPGA die to produce an AI-optimized FPGA. The new FPGA die replaces existing DSP blocks with AI Tensor blocks, tailored for the computations needed in AI workloads. The result was a 15X performance boost for these workloads. Heterogeneous integration allowed Intel to bring the Intel Stratix 10 NX FPGA to market more quickly than might have been possible otherwise and opened a new market segment for Intel. Intel FPGAs are certainly not the only products in Intel’s silicon portfolio to benefit from the company’s advanced packaging technologies. For example, Intel® Core™ Processors with Intel Hybrid Technology, code-named “Lakefield,” were announced in June. These new members of the Intel Core processor family are the industry’s first product to incorporate Intel’s Foveros 3D stacking technology and a hybrid computing architecture. During Architecture Day 2020, Ravi Kuppuswamy - Corporate Vice President and General Manager of Custom Logic Engineering – disclosed that Intel’s next-generation FPGAs would employ both Foveros and Co-EMIB packaging technologies. Kuppuswamy also disclosed a new SerDes test chip, which currently operates at 112 Gbps in NRZ mode and 224 Gbps in PAM4 mode. This new SerDes represents precisely the sort of semiconductor chiplet technology that requires advanced packaging technologies such as Foveros and Co-EMIB to become practical. The critical importance of advanced packaging and heterogeneous integration is not lost on the press and analysts. Here are some observations from various publications, based on the information presented during Architecture Day 2020: “Intel's advanced packaging technologies will allow it to mix and match IP and process nodes from other vendors into the same heterogeneous packages, yielding time to market advantages. The standardized AIB (Advanced Interface Bus) interface is the key that unlocks that level of cooperation and integration between so many disparate partners. Intel has worked to further this once-proprietary standard by contributing it to the open-source CHIPS alliance without requiring royalties or licensing, thus allowing other companies to develop chiplets that are compatible with both Intel and others' chiplets.” – Paul Alcorn, Tom’s Hardware “Related to the future of design and packaging in the industry, which I see as chiplets from many companies coming together in a 3D package, I feel confident Intel is extremely competent, maybe even the current lead. This is a long-term strategy and industry shift… Intel's commitments to improving packaging and IO are among some of the most impressive ways that I see them navigating this new competitive environment and should yield some very interesting products down the road…” - Patrick Moorhead, Forbes “Intel detailed that the EMIB roadmap, with its AIB or Advanced Interface Bus architecture, will scale to a much denser 36 micron bump density and up to 6.4Gbps wire data rate with AIB 2.0. In addition, Intel has made an AIB Generator open source and available on GitHub, to help enable ecosystem partners to develop on the technology as well. Intel calls this “2.5D” packaging technology…” – Dave Altavilla and Marco Chiappetta, HotHardware “What I will say is that if this is truly Intel’s direction, then defining this strategy and building the chiplet ecosystem could be, by far, the most important job at the company.” – Patrick Kennedy, Serve the Home Process and packaging technologies are not all that’s needed to reach the sort of goals that Intel aims to achieve in the quest to move, process, and store everything. Computing workloads have been changing, expanding, as the world finds new ways to harness computing technology. That’s why the XPU architecture concept is the second of Intel’s technology pillars. Intel has characterized four broad computing architectures for the XPU architectural pillar: Scalar: As characterized by the many Intel CPU and processor families Vector: As characterized by the Intel® Xe family of GPUs (extensively discussed during Architecture Day 2020) Matrix: As characterized by the Intel® Habana® Gaudi® and Goya™ AI processor families Spatial: As characterized by Intel FPGA families All of these processing architectures are important in the quest to turn mountains of raw data into usable information and all exist within the Intel semiconductor portfolio. To convert these mountains of data into useful, actionable information, future software programmers need a unified programming environment, architecture, and languages that natively support these four basic computing architectures. That’s why another of the Architecture Day 2020 presentations was devoted to oneAPI, which is Intel’s company-wide effort to develop the unified set of tools needed to deploy applications and solutions across these four computing architectures. We’ll give EEJournal’s Kevin Morris the last word here, from his article titled “No More Nanometers”: “…to really evaluate a semiconductor technology platform, we have to look well beyond the number of transistors we can cram on a monolithic piece of silicon. We need to look at all the elements that define system-level performance and capability and account for all of those. Beyond the usual performance, power, and area of monolithic silicon, we have packaging technology that allows us to stack more (and more varied) die in a single package, interconnect technology that improves the bandwidth between system elements, architectural and structural improvements to semiconductors that are not related to density, new materials that improve the speed and power efficiency – the list goes on and on.” If you’d like to watch the Architecture Day 2020 presentations for yourself, the full video presentation lasting nearly three hours is available here in the Intel Newsroom and the 233-page slide deck used during the presentation is available as a PDF here. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices and Disclaimers Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products. For more complete information visit www.intel.com/benchmarks. Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Performance results are based on testing as of dates shown in configurations and may not reflect all publicly available updates. For testing details and system configurations, please contact your Intel representative. No product or component can be absolutely secure. Results that are based on pre-production systems and components as well as results that have been estimated or simulated using an Intel Reference Platform (an internal example new system), internal Intel analysis or architecture simulation or modeling are provided to you for informational purposes only. Results may vary based on future changes to any systems, components, specifications, or configurations. Intel technologies may require enabled hardware, software or service activation. Intel contributes to the development of benchmarks by participating in, sponsoring, and/or contributing technical support to various benchmarking groups, including the BenchmarkXPRT Development Community administered by Principled Technologies. Statements in this presentation that refer to future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on estimates, forecasts, projections, uncertain events or assumptions, including statements relating to future products and technology and the expected availability and benefits of such products and technology, market opportunity, and anticipated trends in our businesses or the markets relevant to them, also identify forward-looking statements. Such statements are based on management's current expectations and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company's expectations are set forth in Intel's earnings release dated July 23, 2020, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date, and Intel's SEC filings, including the company's most recent reports on Forms 10-K and 10-Q. Copies of Intel's Form 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC's website at www.sec.gov. Intel does not undertake, and expressly disclaims any duty, to update any statement made in this presentation, whether as a result of new information, new developments or otherwise, except to the extent that disclosure may be required by law. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Access leading edge Intel® FPGA Hardware and Software Development Tools for Free on the Intel® DevCloud
Now, you can get access to Intel® FPGA hardware and software development tools, for free, through a special program available on the Intel® DevCloud. These tools allow you to develop accelerated, programmable solutions and validate your workloads on leading FPGA hardware with tools optimized for Intel® technology. The program is open to Intel customers, partners, and academia. The program’s objective is to ensure your success with pre-validated SW environments and a quick start-up while providing timely support to resolve technical barriers that might shorten your time to success. Development takes place on a cluster of the latest Intel® hardware and software. Everything you need to work on your projects is included in the broad portfolio of integrated Intel® optimized frameworks, tools, and libraries available on the Intel DevCloud including the Intel® oneAPI, Intel® OpenCL™, and Intel® OpenVINO™ toolkits, the servers that run the tools, and a collection of Intel® FPGA Programmable Accelerator Cards (PACs) based on Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Registration is required for access. Click here for more information. Intel’s silicon and software portfolio empowers our customers’ intelligent services from the cloud to the edge. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.Free Webinar: Using Intel® oneAPI™ to Achieve High-Performance Compute Acceleration with FPGAs
Interested in learning how to use the Intel® oneAPI™ open, unified programming model to accelerate data-centric workloads using FPGAs? Then sign up for the free Webinar titled “Using Intel oneAPI to Achieve High-Performance Compute Acceleration with FPGAs.” It’s being presented on March 23 and March 25 by Intel and Bittware. The Webinar will zero in a real-world, 2D FFT workload accelerated by BittWare's 520N-MX PCIe acceleration card based on the Intel® Stratix® 10 MX FPGA. This Intel FPGA incorporates high-performance HBM2 memory, which delivers additional acceleration speed. The Webinar will discuss: How the Intel oneAPI unified programming model enables easier, software-like FPGA workload acceleration development A look at BittWare's accelerated 2D FFT code A discussion of various development tools including the Intel® Vtune™ Profiler, which optimizes application performance, system performance, and system configuration for HPC, cloud, IoT, media, storage, and more A preview of next-generation acceleration cards like BittWare's IA-840F, which is based on the Intel® Agilex™ FPGA. A live Q&A with the Webinar’s four panelists from Intel and Bittware Intrigued? Register for either Webinar by clicking the links below: Tuesday March 23: 8:30am UK/4:30am Eastern (time targets EU/Asia) Thursday March 25: 6:30pm UK/2:30pm Eastern (time targets Americas) Note: If you can't make the live event, register anyway and you will get access to the on-demand Webinar recording. Notices & Disclaimers Intel technologies may require enabled hardware, software or service activation. No product or component can be absolutely secure. Your costs and results may vary. Intel does not control or audit third-party data. You should consult other sources to evaluate accuracy. © Intel Corporation. Intel, the Intel logo, and other Intel marks are trademarks of Intel Corporation or its subsidiaries. Other names and brands may be claimed as the property of others.
