Can I program Altera in-system programmable (ISP) devices concurrently?
Description Yes, you can program Altera® devices that support ISP concurrently within a particular device family. When the Joint Test Action Group (JTAG) ISP Clock (TCK) is run at high frequencies (1 to 10 MHz), the time necessary to shift data and address information into the device becomes negligible compared to the programming pulse time for the memory cells. When programming multiple devices in a JTAG chain, concurrent programming allows the programming pulses for each of the devices to be applied simultaneously. Thus, this concurrent programming allows programming times to be significantly reduced. When the TCK is run at low frequencies (~100 kHz), the time necessary to shift data and address information into the device becomes dominant as compared to the programming pulse time for the memory cells. Thus at these lower frequencies, concurrent programming has negligible benefits. Altera supports concurrent programming when using Serial Vector Format files (.svf), Jam™ files (.jam), and Jam Byte-Code files (.jbc). These file formats automatically use concurrent programming whenever more than one device, of the same family, is targeted. For more information, refer to In-System Programmability Guidelines for MAX II Devices (PDF) and AN 100: In-System Programmability Guidelines (PDF).Error: TBBmalloc: skip allocation functions replacement in ucrtbase.dll: unknown prologue for function _msize
Description Due to a problem in the Quartus® Prime Standard Edition Software version 24.1 or earlier, you may see this error message when generating Altera® IP on the Windows* 11 OS (Operating System). Resolution To work around this problem, follow these steps: Go to This PC, right-click, and select Properties. Click Advanced System Setting. In the Advanced tab, select Environment Variable. Under System variables, create a new variable with the name TBB_MALLOC_DISABLE_REPLACEMENT and value as 1. Click OK and restart the Quartus® Prime Software.Why are IBIS models not generated for the PCI IO standard by the Intel® Quartus® II design software when the current strength is set to a minimum?
Description IBIS models are not generated for the PCI I/O standard in Quartus® II if a minimum current strength assignment has been applied, as the PCI I/O standards do not support current strength control. A warning of the form given below will be observed during IBIS file generation if a minimum current strength assignment has been made: Warning: IBIS model for pin "pci_<pin name>" at package pin <pin location> is not available Resolution To work around this issue, remove any current strength assignments made to PCI I/O standard pins and re-compile the design.Why does Questa* license fail to install in the Quartus® Prime Lite Edition Software version 24.1?
Description This problem is due to user setup changed to new NIC ID. The license does not match the current NIC ID. Resolution To workaround this problem, you need to regenerate the license using new NIC ID then update the environment variable method and restart the computer to get the license to operate properly.Why is the input register not registered in the negative input pins, rx_in[*](n) of the ALTLVDS_RX megafunction?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 23.1 and earlier, you might see that the input register is not registered in the ALTLVDS_RX megafunction's negative input pins, rx_in[*](n). This is because the synthesis attributes "LVDS_RX_REGISTER=LOW" and "LVDS_RX_REGISTER=HIGH" are not assigned to the register in the Low-voltage differential signaling (LVDS) receiver interfaces. Resolution To work around the problem, add the following assignments in the Quartus® Settings File (.qsf): set_instance_assignment -name LVDS_RX_REGISTER LOW -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_l_reg" set_instance_assignment -name LVDS_RX_REGISTER HIGH -to "altlvds_rx:ALTLVDS_RX_component|altlvdsrx_lvds_rx:auto_generated|altlvdsrx_lvds_ddio_in:ddio_in|ddio_h_reg" This problem is currently scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.How can I interface the TDI and TDO lines of the JTAG pins of MAX series devices that have different VCCIO levels?
Description You can interface the TDI and TDO lines of the JTAG pins of MAX® series devices that have different V CCIO levels by inserting a level shifter between the devices. Refer to Configuring Mixed Altera FPGA Chains (PDF) for an example of how to interface the TDI and TDO lines of the JTAG pins that have different V CCIO levels.If an Altera® FPGA features MultiVolt I/O interface capability, can VCCIO be varied dynamically without reconfiguring the Altera® FPGA?
Description Altera® FPGAs that feature MultiVolt I/O interface capability, VCCIO must not be varied dynamically or without reconfiguring the device. Resolution However, the power supply voltage of the Altera® FPGA driving the MultiVolt input may be varied dynamically within limits specified in the Altera® FPGA documentation for the chosen value of VCCIO.Does Altera provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI?
Description Altera® does not provide rise and fall time specifications for the JTAG input signals TCK, TMS, and TDI. You can refer to the Input Signal Edge Rate Guidance (PDF) White Paper for further guidance on this topic. Related Articles What is the rise and fall time requirement for the JTAG data (TDO) going to the USB Blaster? What are the recommended rise and fall time specifications for Altera® devices?Which Quartus® Prime versions support the Generic Flash Programmer?
Description Generic Flash Programmer is supported starting from Quartus® Prime Standard Edition software version 18.1.1 and later, and Quartus® Prime Pro Edition software version 19.1 and later. Resolution Generic Flash Programmer is supported starting from Intel® Quartus® Prime Standard Edition software version 18.1.1 and later and Intel® Quartus® Prime Pro Edition software version 19.1 and later.Can I perform multiple compilations at the same time on one computer with a single-seat license?
Description You cannot perform multiple simultaneous compilations using the Quartus® Prime Software if you have a floating license with a single license seat. The number of concurrent compilations that can be run on a single computer cannot exceed the number of available license seats. If you have one fixed (node-locked) license, you can run multiple simultaneous compilations on that machine. Resolution See the related solution below for details on when the Quartus® Prime Software checks for available licenses. Related Articles When is a license checked out by the Quartus II software, IP cores and ModelSim-Altera Edition software?