Why does the text overlap in the ALTPLL IP Parameter Editor?
Description Due to a problem in the Quartus® Prime Standard Edition Software version 25.1, you might see that the text overlaps in the ALTPLL IP Parameter Editor on the Windows* Operating System. This prevents the ALTPLL IP from being instantiated. This problem does not occur in the Quartus® Prime Standard Edition Software version 24.1 and earlier. Resolution To work around this problem in the Quartus® Prime Standard Edition Software version 25.1, download and install the patch below: This problem is scheduled to be resolved in a future release of the Quartus® Prime Standard Edition Software.Why I can't open Early Power Estimators (EPE) tool in the latest version of Microsoft Excel?
Description There is a compatibility issue with the current EPE tools with the latest update from Microsoft* on the Excel version 2505 and later. The update from Microsoft causes the EPE tools to stop working. Resolution There is no plan to fix this. Users need to use the Excel version before version 2505 for the EPE tools to work. There is a workaround if the user needs to use the latest Excel version, please contact Altera support and quote this ID #15018720346How to mitigate the security vulnerability in the Nios® II Command Shell utility?
Description Due to a problem in the Quartus ® Prime Standard and Lite Edition Software version 19.1 through 24.1, the Nios® II Command Shell utility included in the Quartus ® Prime Software for Windows* is vulnerable to a Current Working Directory (CWD) planting attack. The Linux* versions are not affected. Resolution To work around this problem, replace the “Nios II Command Shell.bat” Windows Batch File located in the <drive>:\<edition>\<version number>\nios2eds\, with the attached file below. This problem is fixed beginning with the Quartus® Prime Standard and Lite Edition Software version 25.1.Why does the Nios® V processor that applies fast JTAG UART driver stop (stuck in a loop) when the JTAG UART terminal is not active?
Description Due to a problem in the Board Support Package Editor of Quartus ® Prime software, the JTAG UART driver for fast implementation might get stuck in a loop for any Nios ® V processor designs, when JTAG UART terminal is not active. This problem has been present since: Quartus ® Prime Pro Edition software version 21.3 Quartus ® Prime Standard Edition software version 22.1 It is because the JTAG UART IP is initialized before the Nios ® V processor initialization in alt_sys_init.c. For example: void alt_sys_init( void ) { ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); INTEL_NIOSV_M_INIT (NIOS, nios); } Resolution To work around this problem, update the alt_sys_init.c to initialize the Nios ® V processor first. void alt_sys_init( void ) { INTEL_NIOSV_M_INIT (NIOS, nios); ALTERA_AVALON_JTAG_UART_INIT (JTAG_UART, jtag_uart); } This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime software. Additional Information Refer to Embedded Peripherals IP User Guide [titled as JTAG UART Core - Driver Options: Fast vs. Small Implementations] for more information about the JTAG UART driver for fast (non-blocking) and slow (blocking) implementation. Related Article NIOSV firmware stuck when juart-terminal is not open for the print messages.
Why does the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fail to access a QSPI flash memory device?
Description Due to a problem in multiple Quartus® Prime Pro Edition and Standard Edition software versions, the ASMI Parallel II IP or the Generic Quad SPI Controller II IP fails to access a Quad SPI flash memory device. The affected software versions are: Quartus® Prime Pro Edition software versions from 22.1 to 25.3 Quartus® Prime Standard Edition software versions from 22.1 to 24.1 Chronologically, Prior to version 22.1, the initial state of DATA[3:2] was high. For the affected software versions, the initial state of DATA[3:2] was incorrectly changed to Hi-Z. For reader’s information, some quad SPI flash memory devices support RESET or HOLD function on DATA[3] and WRITE_PROTECT function on DATA[2]. DATA pins can be known as DATA, DQ, IO, or SIO across different QSPI flash memory device vendors. This modification to Hi-Z is recognized as low, thus the active-low RESET, HOLD and WRITE_PROTECT functions are enabled. With these, they prevent the flash controller IP from gaining access to flash devices. Resolution DATA[3:2] must be kept high as the initial state. If the targeted flash device is the Active Serial configuration flash memory, this problem is fixed starting from, Quartus® Prime Pro Edition software version 25.3.1, and Quartus® Prime Standard Edition software version 25.1. Otherwise (i.e. generic-purpose flash memory or affected software version), please refer to the workarounds below. For affected software versions, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2]. Internal weak pull-up resistor option is unavailable for dedicated AS_DATA pins. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project After Quartus® Prime Pro Edition software version 25.3.1 and Quartus® Prime Standard Edition software version 25.1, Targeted Flash Device Workarounds Active Serial configuration flash memory Differentiated with: DATA[3:2] pins are assigned to dedicated AS_DATA[3:2] pins Disable dedicated Active Serial interface option is turned off The initial state of DATA[3:2] is reverted to high. No workaround is needed. Generic-purpose flash memory Differentiated with: DATA[3:2] pins are assigned to generic I/O pins Disable dedicated Active Serial interface option is turned on The initial state of DATA[3:2] is Hi-Z. Add external pull-up registers to the I/O VCC voltage on DATA[3:2], or Enable internal weak pull-up resistor on DATA[3:2] pins in Quartus® design project Related IP Cores ASMI Parallel II IP, Generic Quad SPI Controller II IPWhy does Nios® V processor design fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus® Prime project instead of the QIP file?
Description In the Quartus ® Prime Standard Edition software version 25.1, any Nios ® V processor designs might fail to compile during Analysis & Synthesis when the QSYS file is added into the Quartus ® Prime project. Here are the possible error messages that you might receive: Error (10170): Verilog HDL syntax error at niosv_cpp_fsm.sv(1418) near text: "'"; expecting ":", or "?", or binary operator. Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (16950): Verilog HDL error at : decimal constant 00000000000000010000000000000000 is too large, using 1874919424 instead Error (16814): Verilog HDL error at ... : unknown literal value 00000000000000010000000000000000 for parameter ... ignored This is because the Quartus ® Prime Standard Edition software version 25.1 has been updated to adhere to the software requirements below. This requirement is not mandatory in prior versions of the Quartus ® Prime Standard Edition software. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, Remove the QSYS file from the project using the Remove Files in Project function. Add the QIP file to the project using the Add Files in Project function. Related Articles ERROR building simple NIOS® V Compact project Nios® V Synthesis Fails with Quartus® Prime 25.1 LiteWhy does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system?
Description Due to a problem in the Ashling* RiscFree* IDE for Altera software version 25.2.1 (version dated 9 th May 2025), the Ashling* RiscFree* IDE might fail to detect other Nios ® V processor cores (except Core 0) for Nios ® V processor multicore designs. This is because there is a bug in the Ashling* GDBServer software. Error message: [GDB server output] Error: The device configuration selected has only 1 core (Core 0). Core 1 is not available. Resolution To workaround this issue, please switch from Ashling* GDBServer to Open On-Chip Debugger (OpenOCD) when debugging a Nios ® V multicore processor system. Add the “–o" argument when running niosv-download. niosv-download app.elf -o <options> This problem is scheduled to be fixed, beginning with the Ashling* RiscFree* IDE for Altera software version 25.3.1 (version dated 1 st August 2025).Why does Ashling* RiscFree* IDE for Altera® FPGAs fail to debug a Nios® V processor C++ software project in Windows?
Description Due to a problem with the Ashling* RiscFree* IDE for Altera ® FPGAs software, debugging a Nios ® V processor software project may fail when it is written in the C++ language. This is because there is a bug in the processor toolchain from the Ashling* RiscFree* IDE for Altera ® FPGAs software. C projects are not affected by this issue. You might receive the following error messages. Error Messages How is RISC-V GDB executed? Error in services launch sequence: GDB prompt not read From Ashling* RiscFree* IDE for Altera software ../../../gdb/gdb/cp-name-parser.y:192: internal-error: fill_comp: Assertion ‘i’ failed. Executing riscv32-unknown-elf-gdb commands in the command-line interface The affected Ashling* RiscFree* IDE for Altera ® FPGAs software versions are: 24.3.1 (version dated 9 th Aug 2024) 24.4.0 (version dated 27 th Sep 2024) 25.1.1 (version dated 31 st Jan 2025) Note that: This problem only affects Windows environments. C projects are not affected by this problem. Resolution This problem is fixed beginning with the Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025). You can download Ashling* RiscFree* IDE for Altera ® FPGAs software version 25.2.1 (version dated 9 th May 2025) separately from Quartus® Prime Pro Edition Installer for software version 25.1.1. Follow these steps: Go to the Quartus® Prime Pro Edition Installer for software version 25.1.1 download link. Select Windows as the Operating System. Download the Quartus® Prime Pro Edition Installer for software version 25.1.1. Launch the installation. Select the following files to install: Add-ons and Standalone Software > Ashling* RiscFree* IDE for Altera Add-ons and Standalone Software > Quartus ® Prime Pro Edition Programmer and Tools Note: Refrain from using the Quartus® Prime Pro Edition Installer for software version 25.3 to resolve this problem. The installer contains the older version of the Ashling* software (Software version 25.1.1).Why does Nios® V processor simulation fail when using the generated VHDL testbench from Platform Designer?
Description Due to a problem in the Quartus ® Prime Standard Edition software version 25.1, Nios ® V processor simulation may fail with the generated VHDL testbench system from Platform Designer for any processor design. This problem affects: All Altera ® FPGA device families in Quartus ® Prime Standard Edition software, and All Nios ® V processor variants (Nios ® V/g, Nios ® V/m, and Nios ® V/c processors). It is because the generation of the Nios ® V processor VHDL testbench system is not supported in Quartus ® Prime Standard Edition software version 25.1. Resolution To work around this problem in the Quartus ® Prime Standard Edition Software version 25.1, please select “Verilog” at the “Create testbench simulation model” input option. This problem is currently scheduled to be resolved in a future release of the Quartus ® Prime Standard Edition software. Related Articles 3.3.1. Preparing Hardware Design for SimulationCan I program Altera in-system programmable (ISP) devices concurrently?
Description Yes, you can program Altera® devices that support ISP concurrently within a particular device family. When the Joint Test Action Group (JTAG) ISP Clock (TCK) is run at high frequencies (1 to 10 MHz), the time necessary to shift data and address information into the device becomes negligible compared to the programming pulse time for the memory cells. When programming multiple devices in a JTAG chain, concurrent programming allows the programming pulses for each of the devices to be applied simultaneously. Thus, this concurrent programming allows programming times to be significantly reduced. When the TCK is run at low frequencies (~100 kHz), the time necessary to shift data and address information into the device becomes dominant as compared to the programming pulse time for the memory cells. Thus at these lower frequencies, concurrent programming has negligible benefits. Altera supports concurrent programming when using Serial Vector Format files (.svf), Jam™ files (.jam), and Jam Byte-Code files (.jbc). These file formats automatically use concurrent programming whenever more than one device, of the same family, is targeted. For more information, refer to In-System Programmability Guidelines for MAX II Devices (PDF) and AN 100: In-System Programmability Guidelines (PDF).
