Are there any designations in the Altera part number that signifies if the device operates in the extended industrial temperature range?
Description There are no designations in the Altera® device part number that signifies if the device operates in the Extended Industrial temperature range. Certain Industrial temperature range devices have been qualified for operation over the Extended Industrial temperature range at de-rated frequencies. These devices retain the Industrial temperature range marking "I" in the Operating Temperature field of the Ordering Part Number (OPN). Note that only certain Industrial temperature range part numbers have been qualified for operation over the Extended Industrial temperature range. These qualified devices will operate over the Extended Industrial temperature range as specified. For more information go to the Extended Temperature Device Support page.Can I connect the VCC(TRGT) of the 10-pin download cable header to a different power source which has the same voltage as the recommended power source?
Description Whilst the Altera® device handbooks and download cable user guides say pin 4 of the 10-pin download cable header for VCC(TRGT) needs to be connected to recommended power sources such as VCCIO, VCCA, or VCCPD, you can also connect this to a different power source with the same voltage as the recommended power source.Why does the "Nios® V Command Shell (Quartus® Prime 24.1std)" not work on Windows?
Description Due to the problem of Quartus® Prime Standard Edition Software version 24.1, the path of a shortcut in the Nios® V Command Shell is incorrect. Resolution Search "Nios V Command Shell (Quartus Prime 24.1std)" in Windows Search Box. Right-click and select "Open file location." Right-click on "Nios V Command Shell (Quartus Prime 24.1std)", and select Properties Replace "C:\niosv\bin\niosv-shell.exe" in Target with "C:\altera\24.1std\niosv\bin\niosv-shell.exe" when the install path is default. Additional Information This problem will be fixed in future release of Quartus® Prime Standard Edition Software.When does the Quartus® Prime Design Software, IP cores, and Questa*-Intel® FPGA Edition Software check out a license?
Description Below is a description of how the Quartus® Prime Design Software, IP cores, and Questa*-Intel® FPGA Edition Software utilize licenses: Resolution Quartus® Prime Design Software: All Quartus® Prime Design Software processes check for a valid license, including the Quartus® GUI, Analysis & Synthesis, Assembler, and TimeQuest Timing Analyzer. These processes start only if a valid license is available. They do not hold or occupy the license; they only validate that one is available. However, the Fitter checks out a license when it starts and holds it for the duration of the Fitter process. IP cores: A license for an IP core is checked out when the Quartus® Prime Design Software opens the first encrypted file of the IP core for synthesis. This license is held for the duration of synthesis. The Assembler checks out the license for every IP core to create the programming file and holds it for the duration of the Assembler process. Questa*-Intel® FPGA Edition software: Once Questa*-Intel® FPGA Edition Software loads a design unit during elaboration, a Questa-Intel® FPGA Edition license is checked out. It remains checked out until the simulation ends (quit -sim), or the simulator is closed. Once a waveform is loaded into the simulator, a Questa*-Intel® FPGA Edition Software license is also checked out for viewing Wave Log Format File (.wlf), and it remains checked out until the waveform window is closed. Related Articles What happens to a license if the Quartus II software terminates unexpectedly? Can I perform multiple compilations using the Quartus II software at the same time on one computer with a one seat floating license or one fixed (node locked) license file?How do I force the SRAM download for the MAX® II, MAX V and MAX 10 device after real time In-System Programming (ISP), without a power cycle?
Description To force the SRAM download after real time ISP with the download.jam file and the Jam ™ Standard Test and Programming Language (STAPL) player, type the following line in the command prompt: jam -aSRAM_DOWNLOAD download.jam where jam is the executable file of the Jam STAPL player. To force the SRAM download after real time ISP with the download.jbc file and the Jam STAPL Byte-Code (JBC) player, type the following line in the command prompt: jbi -aSRAM_DOWNLOAD download.jbc where jbi is the executable file of the JBC player. If using the quartus_jli executable, the command would be: quartus_jli -cn -aSRAM_DOWNLOAD download.jam or quartus_jli -cn -aSRAM_DOWNLOAD download.jbc where <n> after -c is the download cable index. Alternatively, you may also use the download.svf file and execute the force SRAM download function in the JTAG Chain debugger tool in the Quartus II software as follows: 1. From Processing menu open the JTAG Chain Debugger tool 2. Go to JTAG Chain Debugging tab and click the Open JTAG Chain Log file button 3. Select the download.svf file which contains the force download instruction The SVF file can also be used with a 3rd Party programming tool. Related Articles What happens to the MAX II input/output (I/O) pins during a Real-Time in-system programming (ISP) update?Why is the output latency of the Status Flags for the DCFIFO IP higher than the latency specified in the SCFIFO and DCFIFO IP Cores User Guide?
Description Due to the cross-clocking nature of the DCFIFO IP, the latency of the Status Flags could be 1 greater than that specified in the SCFIFO and DCFIFO IP Cores User Guide (PDF).What is the part marking format for MAX V devices in the M100 package?
Description Due to the small size of the M100 package used by MAX® V devices, the top-side marking format is different to the standard BGA marking format. The following text is shown in the centre of the top side: ALTERA 5M570Z M100I5N Date code The lot and trace codes are written on the bottom and left edges of the device.Are there any known issues using the Intel® FPGA Download Cable II with MAX® II or MAX® V devices?
Description The frequency of the Intel® FPGA Download Cable II (formerly the USB-Blaster II) defaults to 24 MHz. This frequency exceeds the maximum TCK frequency specification of MAX® II and MAX® V devices. Operating at this frequency may result in detection or programming issues if a MAX II or MAX V device is the target or is in the JTAG chain with other Intel® FPGAs. Resolution If using the Intel® FPGA Download Cable II with MAX® II or MAX® V devices, set the frequency of the cable to less than 24 MHz (e.g. 16 MHz or less). Related Articles How do I change the clock frequency of the USB-Blaster II download cable? Why does the TCK frequency setting of the USB-Blaster II download cable revert to the default value of 24 MHz after being changed?