Knowledge Base Article

Why is the output latency of the Status Flags for the DCFIFO IP higher than the latency specified in the SCFIFO and DCFIFO IP Cores User Guide?

Description
Due to the cross-clocking nature of the DCFIFO IP, the latency of the Status Flags could be 1 greater than that specified in the SCFIFO and DCFIFO IP Cores User Guide (PDF).
Updated 7 days ago
Version 2.0
Arria® 10 FPGAs and SoCs
Arria® II FPGAs
Arria® V FPGAs and SoCs
Cyclone® IV FPGAs
Cyclone® V FPGAs and SoCs
MAX® 10 FPGAs
MAX® II CPLDs
MAX® V CPLDs
Stratix® IV FPGAs
Stratix® V FPGAs
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