How can I port RTL module into oneAPI FPGA programming ?
Hi there, I have been using oneAPI for FPGA programming for a while. I am now trying to port my well-defined RTL module into my oneAPI implementation. I do read and understand the specification documents provided in oneAPI websites also the openCL SDK development. However, one of these have pointed a very clear way to interact with RTL module using oneAPI. I am successfully runing a combinational vector-add sample myself, but have no idea how to interact with the sythesized modules from oneAPI with clock driven capability and Avalon-ST interface. Have anyone done such a tryout before ? Best.
