Can I connect VCCIO of I/O bank 1 to 2.5 V for AS configuration with EPCQ or EPCQA device when using Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device?
Description No, when you use EPCQ or EPCQA quad-serial configuration device for AS configuration, you cannot connect VCCIO of I/O bank 1 to 2.5 V in Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device. This is because the minimum VOH of the FPGA is insufficient for driving EPCQ or EPCQA input pins. Resolution Use 3.0 V or 3.3 V for Bank 1 VCCIO in Cyclone III, Cyclone IV, and Intel Cyclone 10 LP devices when AS configuration with EPCQ or EPCQA devices is used.Are there any designations in the Altera part number that signifies if the device operates in the extended industrial temperature range?
Description There are no designations in the Altera® device part number that signifies if the device operates in the Extended Industrial temperature range. Certain Industrial temperature range devices have been qualified for operation over the Extended Industrial temperature range at de-rated frequencies. These devices retain the Industrial temperature range marking "I" in the Operating Temperature field of the Ordering Part Number (OPN). Note that only certain Industrial temperature range part numbers have been qualified for operation over the Extended Industrial temperature range. These qualified devices will operate over the Extended Industrial temperature range as specified. For more information go to the Extended Temperature Device Support page.Why do I get a fatal error when creating an ALTPLL IP?
Description Due to a problem in the Quartus® Standard Edition Software version 23.1, you might see a fatal error when creating an ALTPLL IP Using the MegaWizard Plug-In Manager. Resolution To work around this problem, download and install the patches below for the Quartus® Prime Standard Edition Software version 23.1 Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Windows (.exe) Quartus® Prime Standard Edition Software v23.1 Patch 0.02std for Linux (.run) Readme for Quartus® Prime Standard Edition Software v23.1 Patch 0.02std (.txt) This problem is scheduled to be fixed in a future release of the Quartus® Prime Standard Edition Software.Internal Error: Sub-system: ASM, File: /quartus/comp/asm/asm_split_bits_utility.cpp, Line: 621 Bad mask!
Description Due to a problem in the Quartus® II software version 13.1 and earlier, you may see this error when compiling a Cyclone® IV or Cyclone V design using the Functional Safety Separation Flow. During partition import of strictly preserved safety partitions, routes to top-level safe IO buffers are not correctly preserved. When the Assembler detects the preservation mismatch during the Design Modification Flow it fails with this internal error. Resolution To work around this problem, for the Quartus II software version 13.1 Update 4, download and install patches 4.30 and 4.55 from the links below. You must install the Quartus II software version 13.1 Update 4 before installing these patches. Download the Quartus II software version 13.1 Update 4 patch 4.30 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.30 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.30 (.txt) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Windows (.exe) Download the Quartus II software version 13.1 Update 4 patch 4.55 for Linux (.run) Download the Readme for the Quartus II software version 13.1 Update 4 patch 4.55 (.txt) For the Quartus II software version 14.1 Update 1, download and install patch 1.04 from the links below. You must install the Quartus II software version 14.1 Update 1 before installing this patch. Download the Quartus II software version 14.1 Update 1 patch 1.04 for Windows (.exe) Download the Quartus II software version 14.1 Update 1 patch 1.04 for Linux (.run) Download the Readme for the Quartus II software version 14.1 Update 1 patch 1.04 (.txt) This problem is fixed beginning with version 15.0 of the Quartus II software.How do I determine the phase shift and duty cycle for the required clocks if I am using ALTLVDS_RX and ALTLVDS_TX in external PLL mode?
Description You can determine the phase shift and duty cycle for the required clocks when using ALTLVDS_RX and ALTLVDS_TX in external PLL mode by first compiling an example design with ALTLVDS_RX or ALTLVDS_TX using an internal PLL. Use the settings that the Quartus® II software uses to configure the internal PLL in the example design as the settings you enter in the external PLL. To check the PLL settings in the Fitter report, expand the Resource section, and then expand PLL Usage. The report shows the duty cycle, phase shift and clock frequency for each of the required clocks for the ALTLVDS_RX and ALTLVDS_TX interfaces. You can then use these parameters for the external PLL settings in your design. Related Articles How do I implement ALTLVDS in External PLL Mode for Stratix V, Arria V, and Cyclone V devices? How do I implement the ALTLVDS_RX and ALTLVDS_TX megafunctions with External PLL mode in Arria II GX devices? How do you implement the altlvds megafunction with the External PLL option in Stratix III devices?Timing Analysis for PCI Express Compiler × Variations That Target a Cyclone IV GX Device
Description The Quartus II software does not perform timing analysis for the FPGA fabric in Cyclone IV GX × variants; consequently, variants that would fail timing analysis are not identified. This issue affects × variants in the Cyclone IV GX device. Resolution You can manually create the required clock constraint. provides the equation for this constraint. In this equation <n> is 8.000 for a 125 MHz application clock and 16 for a 62.5 MHz application clock. Clock Constraint # create_clock -name {core_clk_out} -period <n> -waveform { 0.000 8.000 } [get_nets {*altpcie_hip_pipen1b_inst | core_clk_out~clkctrl}] This issue is fixed in version 10.1 of the Quartus II software.Do I need to drive fftpts_in of the FFT Intel® FPGA IP core even if I'm not changing the block size?
Description You may receive source errors (missing SOP, missing EOP) when attempting to process data through the FFT Intel® FPGA IP core when fftpts_in not being driven or being driven incorrectly. Resolution fftpts_in must be driven, even if one is not dynamically changing the block size. For a fixed block size implementation, it should be driven to match the transform length selected in the parameter editor.Can I enable multiple controllers clock sharing in ALTMEMPHY-based High-Performance Memory Controller for Cyclone® III and Cyclone® IV device?
Description Multiple controllers clock sharing option allows the controllers to share the static PHY clocks between multiple controllers that run on the same frequency and must share the same phase-locked loop (PLL) reference clock. However, there is a limitation if you would like to enable this feature on Cyclone® III and Cyclone IV device family. For design with two ALTMEMPHY instances, two PLLs will still be utilized. This is explained in the following knowlegde article: Can I share a single PLL for two ALTMEMPHY instances in my design? For ALTMEMPHY-based memory controller, PLL should be fed on its fully compensated dedicated input pin to reduce Jitter and this is one of the timing model assumptions for PLL and clock network. "The reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL. To minimize output clock jitter, the reference input clock pin to the ALTMEMPHY PLL must not be routed through the core using global or regional clock networks." Cyclone III and Cyclone IV devices do not have fully compensated dedicated clock input that could feed two PLLs. Such PLL clock network is only available on Arria® II GX, Stratix® III, and Stratix® IV device family. Arria II GX device - CLK[8..11] for PLL_5 and PLL_6 Stratix III, Stratix IV device - CLK[0..3] for PLL_L2 and PLL_L3 - CLK[4..7] for PLL_B1 and PLL_B2 - CLK[8..11] for PLL_R2 and PLL_R3 - CLK[12..15] for PLL_T1 and PLL_T2 For these reasons, multiple controllers clock sharing should not be used on Cyclone III and Cyclone IV device family. Resolution Consider having separate clock input for each memory controllers on Cyclone III and Cyclone IV device.How can I select which type of PLL will be used in a Cyclone® IV GX design?
Description Cyclone® IV GX devices have two types of PLLs - multi-purpose PLL (MPLL) and general-purpose PLL (GPLL). The Quartus® II software will automatically select the PLL type based on device usage and resources. If you wish to specify a particular PLL for your design, you can use the Assignment Editor and add location assignments to your PLL instances. The syntax for the location value would be PLL_1, PLL_2, etc. The .qsf syntax to assign a PLL instance to location PLL_1 is: set_location_assignment PLL_1 -to "<instance name>:inst|altpll:altpll_component" Resolution Refer to Clock Networks and PLLs in Cyclone® IV Devices (PDF) to understand which PLL numbers correspond to MPLLs and GPLLs in your device.