Can I connect VCCIO of I/O bank 1 to 2.5 V for AS configuration with EPCQ or EPCQA device when using Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device?
Description No, when you use EPCQ or EPCQA quad-serial configuration device for AS configuration, you cannot connect VCCIO of I/O bank 1 to 2.5 V in Cyclone® III, Cyclone® IV, or Intel® Cyclone® 10 LP device. This is because the minimum VOH of the FPGA is insufficient for driving EPCQ or EPCQA input pins. Resolution Use 3.0 V or 3.3 V for Bank 1 VCCIO in Cyclone III, Cyclone IV, and Intel Cyclone 10 LP devices when AS configuration with EPCQ or EPCQA devices is used.Is there a known issue with the Triple Speed Ethernet (TSE) LVDS Receive (Rx) and Transmit (Tx) general purpose PLLs merging in Quartus II software version 10.1?
Description Yes, the Triple Speed Ethernet IP has enhanced the LVDS Rx PLL reset sequence in Quartus® II software version 10.1. The LVDS Rx PLL now has pll_areset controlled via the tse_lvds_reset_sequencer, whilst the Tx PLL has its pll_areset tied inactive. As the input sources to the two PLLs are now different, Quartus II is no longer able to merge the two PLLs. This issue will be address in a future version of the IP.Why does the Fitter report show an incorrect "OCT_100ohms" receiver termination when external termination is used for Cyclone IV devices with Quartus II software versions 15.0 and earlier?
Description Due to a problem in the Quartus® II software versions 15.0 and earlier, the Fitter will incorrectly report a termination of "OCT_100ohms" on Cyclone® IV GX device receiver input pins when it has been disabled in the Quartus II software. Resolution When disabled in the Quartus II software, the Fitter report\'s termination value is incorrect and can be ignored. The on-chip termination will disabled as intended. This problem is scheduled to be fixed in a future release of the Quartus II software.Is the hard transceiver 8B/10B encoder/decoder in Stratix, Arria, and Cyclone family transceiver devices Fibre Channel compliant?
Description No, the 8B/10B encoder/decoder does not satisfy all the requirements for the Fibre Channel protocol in Stratix® GX, Stratix II GX, Stratix IV GX/T, Arria® GX, Arria II GX, or Cyclone® IV GX devices. 1) Fibre Channel protocol requirements for 1.062 and 2.125 Gbps states that the transmitter needs to start up with negative running disparity. Further, the standard has disparity rules for Ordered Sets. -The embedded 8B/10B encoder does start up with negative disparity. However, the encoder does not contain the functionality to force negative current running disparity at any time. This is required to be able to meet the disparity rules for Ordered Sets. 2) Fibre Channel protocol requirements for "Detection of Invalid transmission Word" for 1.062 and 2.125 Gbps state that Ordered Sets received with incorrect beginning running disparity be flagged as an error. -The current 8B/10B implementation determines running disparity on a character-by-character basis and not Ordered Sets. Due to these non-compliances, customers may or may not be able to use the embedded 8B/10B encoder/decoder in the transceiver megafunction. This decision would have to be based on how the customer is implementing their Fibre Channel or Fibre Channel-like architecture. Possible workarounds: User would have to implement 8B/10B encoding and decoding blocks in the PLD core to be able to meet the specific requirements in both the transmit and receive directions. User could use 8B10B Encoder/Decoder MegaCore Function from Altera Corporation User could use Multi-Gigabit Fibre Channel Transport Core from MorethanIP References: Fibre Channel, Physical Signaling Interface (FC-PH) REV 2.13 December 4, 1991 Fibre Channel Framing and Signaling (FC-FS) REV 1.90Why do I get the error “Error (176286): Found 2 SPI blocks in design” when using Serial Flash Loader Intel® FPGA IP and ASMI Parallel II Intel FPGA IP?
Description This error may be seen if Serial Flash Loader IP and ASMI Parallel II IP is used together in the same design. Both of Serial Flash Loader IP and ASMI Parallel II IP core require ASMI interface access. Therefore, by having both IPs in the same design would cause conflict during compilation as both IPs cannot access the ASMI block at the same time. Resolution To work around this problem, follow the steps below: Turn ON the “Share ASMI interface in the design” check box in Serial Flash Loader IP parameter. Turn ON the “Disable dedicated Active Serial Interface” check box in ASMI Parallel II IP parameter. Route ASMI signals from the ASMI Parallel II IP and connect to the Serial Flash Loader IP ASMI input/output port. Hence, both IPs should be able to share the single ASMI block within Serial Flash Loader IP.Why is the "Enable input tri-state on active configuration pins in user mode" option disabled in the Quartus® II software version 10.0?
Description Due to a problem in the Quartus® II software version 10.0, the Enable input tri-state on active configuration pins in user mode option on the Configuration panel of the Device and Pin Options dialog box is disabled for Cyclone® III, Cyclone® III LS, Cyclone® IV E, Stratix® III, and Stratix® IV devices. Resolution To work around this problem, you can enable this option by adding the following assignment to your Quartus II Settings File (.qsf): set_global_assignment -name TRI_STATE_SPI_PINS ON This problem is scheduled to be fixed in a future release of the Quartus II software. Related Articles How do I assign dual-purpose pins to be a user I/O after configuration in Quartus II software version 10.0?Compiler might be unable to place a refclk pin in a location that feeds the transceiver PLLs for Cyclone IV GX
Description For designs that target Cyclone IV GX devices, the Compiler might be unable to place a refclk pin in a location that feeds the transceiver PLLs Resolution Use location assignments to place the refclk pin and the PLL.Can I leave unused transceiver receivers unconnected for Stratix IV GX/ GT, Arria II GX/GT and Cyclone IV GX devices?
Description The Pin Connections Guidelines document for Stratix® IV GX/GT, Arria® II GX/GZ, and Cyclone® IV GX devices, recommends to connect unused GXB_Rx and REFCLK pins to GND through 10k resistors. The reason for this recommendation is to improve noise immunity. However for applications where the receiver or REFCLK is routed to an unused connector, the receiver would effectively be floating. In this instance it is OK to not tie the unused receiver to GND through a 10k resistor.Error (113029): Data size does not match the number of bytes at line <your line number> in Hexadecimal (Intel-Format) File "<your hex file>.hex" displays when I compile my FFT core design.
Description Due to a problem in the Intel® Quartus® Prime Software, you will see the above error message for certain width inputs to your FFT IP core. Specifically, this error will display if you select either 28 or 32 bits as your Data Input or Twiddle Width in the parameterization GUI. Resolution There is no workaround for this problem for 28 or 32-bit widths; selecting smaller widths will avoid the problem. This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 18.0 and Intel® Quartus® Prime Standard Edition Software version 18.0.Warning (169180): Following pins must use external clamping diodes.
Description You may see the above warning message when you use the configuration pin (also known as dual purpose pin) because the internal clamp diode is not supported on configuration pins in Cyclone® III and Cyclone IV devices. The dual purpose configuration pins do have PCI clamp diode in user mode and that the need for external clamp diodes are to protect the device when there is an overshoot from the configuration device. The external clamp diode is required if the voltage overshoot might exceed the recommended maximum limits.